JPS62243441A - Data reception control equipment - Google Patents

Abstract

PURPOSE:To attain the data transmission by the DMA system even when the data number is not set by sending a DMA request signal to a DMA controller when a coincidence signal generated at the coincidence of a terminator from a data bus with a terminator set in a terminator set device is not outputted. CONSTITUTION:A processor 1 sets a terminator to a terminator setting device 6. When an ATN signal is at H and a DNV signal is at L, the terminator representing the end of transmission of a data is sent from a data bus DB 2 and a comparator 7 sends a terminator coincidence signal S1 to a gate circuit 8. In receiving a coincidence signal S1, the gate circuit 8 closes the gate and the circuit 8 sends a DNA request signal S2 sent from a GPI controller 3 to a DMA controller 2 when the signal S1 is not received and no terminator is sent from the data bus DB2, then the data transmission by the DMA system is applied without setting the data number received in advance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data reception control device used when transferring data according to a DMA method.

[Prior Art] A conventional DMA data reception control device will be described with reference to FIG.

Here, direct memory access (DMA) is I1
A control device (D
This is a method in which a control bag device (MA controller) is provided, and this control bag device directly transfers data block by block between the main storage device and the I10 device at high speed according to commands given from the CPU.

Figure 2 is a block diagram of a conventional MA data reception control device. In Figure 0, (1) is a processor, (2) is a DMA controller that controls the DMA system during data transfer, and (3) is an input G P-I, which manages data transfer when transferring data between external devices such as output devices
B controllers (4) and (5) are ROM and RAM as external storage, respectively. These devices are interconnected via a data bus DB2.

Next, the operation of data transfer using the DMA method using the conventional data reception control device configured as described above will be explained.

First, when a need for DMA transfer arises, the processor (1) sets information necessary for data transfer, such as the number of bytes of data to be transferred and the transfer start address on memory, in the DMA controller (2).

Here, in accordance with the data transfer request sent via the data bus DB2, the G P-I B controller (3)
DMA request signal S to MA controller (2)
2, the DMA controller (2) outputs a signal to request the processor (1) to use the bus,
The processor (1) is apparently separated from the data bus DB2'.

The Standard Interface Bus for Programmable Instruments, or GP-IB, is the International Electrotechnical Commission (IEC).
International Electrotecb
This is the name of a bus standardized as a standard interface for measuring instruments in the field of general measuring instruments in the International Instrumentation Commission.

Then, the DMA controller (2) directly transfers data without going through the processor (1) based on the information set by the processor (1) in advance. When the data transfer using the DMA method is completed, the DMA controller (2) transfers data directly to the processor (1). The signal for requesting use of the bus is released, and the state in which the processor (1) is connected to the data bus DB2 is restored.

[Problems to be Solved by the Invention] Since the data reception control device in the conventional DMA system was configured as described above, it is difficult to transfer the transferred data by DMA.
When receiving data using this method, the receiver had to receive the transferred data according to the preset number of received data.

However, in general, the number of received data is rarely known, and conventional data reception control devices that set the number of transfer bytes of received data and transfer data according to the set number of transfer bytes use the DMA method. There were restrictions on transfer. The present invention has been made to solve the above problems, and an object of the present invention is to provide a data reception control device that can transfer data using a high-speed DMA method even if the number of received data is not known in advance.

[Means for Solving the Problems] Therefore, the data reception control device according to the present invention includes a terminator setting device in which a data terminator is set in advance by a processor, and a terminator and terminator setting device that are sent from a data bus. a terminator comparator that outputs a terminator match signal when they match with the terminator set in G;
The present invention is characterized by comprising a gate circuit that passes a DMA request signal sent from the P-I B controller and transmits it to the DMA controller only when the terminator match signal is not output.

[Operation] A terminator is set in advance in the terminator setting device 6 in the present invention by the processor 1.

Here, when a terminator is sent from the data bus DBZ, the terminator comparator 7 compares the terminator sent from the data bus DB2 with the terminator set in the terminator setter 6. A terminator match signal S1 is output.

Based on the terminator match signal 31, the gate circuit 8 passes the DMA request signal S2 sent from the GPI B controller 3 and transmits it to the DMA controller 2 only when the terminator match signal S1 is not output. .

[Example] The present invention will be described in detail below based on one drawing.

FIG. 1 is a configuration diagram showing an embodiment of the present invention, in which (1) to 5) are the same components as in the prior art, and (6) are the same components as in the prior art.
) is a terminator setting device that sets the terminator sent from the processor (1), and (7) is a terminator that is sent from the data bus DB2 and the terminator set in the terminator setting device (6). A terminator comparator (8) outputs a terminator match signal Sl when they match, and a terminator comparator (8) is a DMA signal that is output from the G P-I B controller (3) only when the terminator negative signal S1 is not output. Request signal S2
A gate circuit (9) controls whether or not to cancel the terminator negative signal Sl output from the terminator comparator (7) and to detect the terminator. and DMA
DMA on/off to control operation by method
This is a controller that outputs the f signal S5 to the gate circuit 8.

Next, the present invention configured as described above will be explained in detail.

First, the processor (1) sets a terminator to the terminator setting device (6) via the internal data bus DBI.

This terminator is a control signal indicating the end of data transferred by the DMA method, and if there are multiple terminators, it is possible to set a plurality of them.

Here, when the ATN signal is "high" (data mode) and the DAV signal is "low" (data valid), a terminator indicating the end of data transfer is sent from data bus DB2. , the terminator comparator (7) outputs a terminator negative signal S1 and transmits it to the gate circuit (8).

The gate circuit (8) closes the gate while receiving the terminator negative signal S1, so that even if the DMA request signal S2 is output from the G P-I B controller (3), it will not be transmitted to the DMA controller (2). I have to.

In this way, while the terminator is not sent from the data bus DB2, the DMA controller (2) accepts the DMA request signal S2 sent from the GP-IB controller (3), thereby allowing the number of data to be received in advance. To enable data transfer by DMA method even without setting.

After the predetermined operation is completed, the terminator negative signal Sl output from the terminator comparator (7) is canceled by the terminator match clear signal S3 output from the controller (9).

Note that while the controller (9) is outputting the terminator detectable/unable signal S4 to the terminator comparator (7) to output the terminator detectable/unable signal, data transfer using the DMA method similar to the conventional one is performed. You may also be able to do this.

In addition, when using data transfer other than DMA method, the controller (9) sends DMA on, off to the gate circuit (8).
The gate circuit (8) may be kept in a closed state when the f signal is output and data transfer is performed using a method other than the DMA method.

In addition, by transmitting the terminator negative signal S1 to the processor (1), it is used as an interrupt signal for the processor (1).
) may perform predetermined processing.

For example, the configuration is such that it means the end of data transfer using the DMA method only when a plurality of terminators are sent from the data bus DB2, and the terminator setting device (6
), and when this last terminator is sent from the data bus DB2 and a terminator-negative signal S1 is transmitted to the processor (1), the processor (1) ) checks whether multiple terminators have been sent and
It may be determined whether or not data transfer using the MA method has been completed.

[Effect of the invention].

As described above, this invention is configured to detect the terminator sent from the data bus and control the DMA request signal output from the GPI B controller, so the number of data to be sent can be determined in advance. , even if you don't know.

Data transfer using the DMA method becomes possible, and there is an effect that high-speed data transfer can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data reception control device showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data reception control device. (1)... Processor, (2)... DMA controller, (3)... G P-I B controller, (6
)...Terminator setting device, (7)...Terminator comparator, (8)...Gate circuit, (9)...Controller. Patent applicant: Anritsu Corporation

Claims (1)

[Claims] Compares the terminator set by the processor with the terminator sent from the data bus and the terminator set in the terminator setter, and outputs a terminator match signal when they match. Terminator comparator and G
A data reception control device comprising: a gate circuit that passes a DMA request signal sent from a P-IB controller and transmits it to the DMA controller only when the terminator match signal is not output.