JPS62230040A - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPS62230040A
JPS62230040A JP61074900A JP7490086A JPS62230040A JP S62230040 A JPS62230040 A JP S62230040A JP 61074900 A JP61074900 A JP 61074900A JP 7490086 A JP7490086 A JP 7490086A JP S62230040 A JPS62230040 A JP S62230040A
Authority
JP
Japan
Prior art keywords
circuit
input
output
terminal
sequential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61074900A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0577292B2 (enExample
Inventor
Hideki Matsuura
英樹 松浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61074900A priority Critical patent/JPS62230040A/ja
Publication of JPS62230040A publication Critical patent/JPS62230040A/ja
Publication of JPH0577292B2 publication Critical patent/JPH0577292B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP61074900A 1986-03-31 1986-03-31 半導体集積回路 Granted JPS62230040A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61074900A JPS62230040A (ja) 1986-03-31 1986-03-31 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61074900A JPS62230040A (ja) 1986-03-31 1986-03-31 半導体集積回路

Publications (2)

Publication Number Publication Date
JPS62230040A true JPS62230040A (ja) 1987-10-08
JPH0577292B2 JPH0577292B2 (enExample) 1993-10-26

Family

ID=13560721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61074900A Granted JPS62230040A (ja) 1986-03-31 1986-03-31 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS62230040A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245971A (ja) * 1988-08-05 1990-02-15 Nec Corp 半導体集積論理回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0245971A (ja) * 1988-08-05 1990-02-15 Nec Corp 半導体集積論理回路

Also Published As

Publication number Publication date
JPH0577292B2 (enExample) 1993-10-26

Similar Documents

Publication Publication Date Title
KR900006484B1 (ko) Ic평가회로 소자와 평가회로 소자 검사수단을 갖는 반도체 집적회로
EP0364925A1 (en) Semiconductor integrated circuit having i/o terminals allowing independent connection test
EP0297821A3 (en) Semiconductor integrated circuit device having gate array and memory
JPH0450678A (ja) テスト容易化回路
KR940025183A (ko) 액티브-레벨로 배치가능한 핀을 갖는 집적회로 및 그 배치 방법
US5796266A (en) Circuit and a method for configuring pad connections in an integrated device
JPS62230040A (ja) 半導体集積回路
US6578168B1 (en) Method for operating a boundary scan cell design for high performance I/O cells
EP0633529A1 (en) Emulation system for microcomputer
US4814639A (en) Super integration circuit device having a plurality of IC-chip equivalent regions formed on a single semiconductor substrate
US6567944B1 (en) Boundary scan cell design for high performance I/O cells
EP1227502A1 (en) Connection pad arrangements for electronic circuit comprising both functional logic and flash-EEPROM
JPH06201794A (ja) 半導体装置のテスト回路
JP2785748B2 (ja) 双方向入出力バッファ
KR910007412B1 (ko) 시험능력을 가진 메가 셀 방식의 집적회로
KR100604785B1 (ko) 바운더리 스캔 셀을 구비하는 집적회로 장치
JPH02112777A (ja) 半導体集積回路
JPH05256915A (ja) マルチチップ実装体
JPH03150484A (ja) 半導体装置
JPS59128464A (ja) 半導体集積回路のテスト入力回路
JPH03185756A (ja) 半導体集積回路装置
JPH01205346A (ja) 半導体集積回路
JPH0727827A (ja) モジュールおよびそれを用いた半導体集積回路装置
JPH0290650A (ja) 半導体装置
JPS60174963A (ja) 電子パツケ−ジ試験回路

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term