JPS6222449B2 - - Google Patents

Info

Publication number
JPS6222449B2
JPS6222449B2 JP9294779A JP9294779A JPS6222449B2 JP S6222449 B2 JPS6222449 B2 JP S6222449B2 JP 9294779 A JP9294779 A JP 9294779A JP 9294779 A JP9294779 A JP 9294779A JP S6222449 B2 JPS6222449 B2 JP S6222449B2
Authority
JP
Japan
Prior art keywords
lead
metallized
bonding
grounding
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9294779A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5617049A (en
Inventor
Katsuhiko Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9294779A priority Critical patent/JPS5617049A/ja
Publication of JPS5617049A publication Critical patent/JPS5617049A/ja
Publication of JPS6222449B2 publication Critical patent/JPS6222449B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
JP9294779A 1979-07-20 1979-07-20 Semiconductor device Granted JPS5617049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9294779A JPS5617049A (en) 1979-07-20 1979-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9294779A JPS5617049A (en) 1979-07-20 1979-07-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5617049A JPS5617049A (en) 1981-02-18
JPS6222449B2 true JPS6222449B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1987-05-18

Family

ID=14068658

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9294779A Granted JPS5617049A (en) 1979-07-20 1979-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5617049A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
JPS5617049A (en) 1981-02-18

Similar Documents

Publication Publication Date Title
US8067823B2 (en) Chip scale package having flip chip interconnect on die paddle
US5384488A (en) Configuration and method for positioning semiconductor device bond pads using additional process layers
JPH09307051A (ja) 樹脂封止型半導体装置及びその製造方法
JP2569400B2 (ja) 樹脂封止型半導体装置の製造方法
JPS6222449B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPH0590486A (ja) 半導体装置
JP2646989B2 (ja) チップキャリア
JP3394480B2 (ja) 半導体装置
US20190206785A1 (en) Electronic devices with bond pads formed on a molybdenum layer
JPS62196839A (ja) ハイブリツド型半導体装置
JPH11265964A (ja) 半導体装置とその製造方法
JPH09252020A (ja) 半導体装置およびその製造方法
KR100362501B1 (ko) 반도체장치
JPH05347324A (ja) 半導体パッケージ
JPH0414503B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS639749B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS5928049B2 (ja) 半導体装置のリ−ド接続方法
JPH0481859B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP4575928B2 (ja) 半導体装置
JP2783089B2 (ja) セラミック型半導体装置
JPH03178140A (ja) 樹脂封止型半導体装置
KR100337458B1 (ko) 반도체패키지의 제조 방법
JPS6336686Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JPS6159846A (ja) 半導体装置
JPH0368156A (ja) 半導体用パッケージ