JPS6221545U - - Google Patents

Info

Publication number
JPS6221545U
JPS6221545U JP1985112778U JP11277885U JPS6221545U JP S6221545 U JPS6221545 U JP S6221545U JP 1985112778 U JP1985112778 U JP 1985112778U JP 11277885 U JP11277885 U JP 11277885U JP S6221545 U JPS6221545 U JP S6221545U
Authority
JP
Japan
Prior art keywords
package
integrated circuit
semiconductor integrated
terminal
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985112778U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985112778U priority Critical patent/JPS6221545U/ja
Publication of JPS6221545U publication Critical patent/JPS6221545U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案による半導体集積回路用パツケ
ージの一実施例の斜視図、第2図は第1図のX―
X′線に沿つた断面図である。 1……パツケージ、7……パツケージ端子穴、
8……実装用パツケージ端子、9……端子接触部

Claims (1)

    【実用新案登録請求の範囲】
  1. 複数の実装用パツケージ端子を備えた半導体集
    積回路用パツケージにおいて、上記実装用パツケ
    ージ端子と電気的に接続された端子接触部を有し
    、上記端子接触部はパツケージ端子穴内にあつて
    外部から接触可能に設けられていることを特徴と
    する半導体集積回路用パツケージ。
JP1985112778U 1985-07-23 1985-07-23 Pending JPS6221545U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985112778U JPS6221545U (ja) 1985-07-23 1985-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985112778U JPS6221545U (ja) 1985-07-23 1985-07-23

Publications (1)

Publication Number Publication Date
JPS6221545U true JPS6221545U (ja) 1987-02-09

Family

ID=30993968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985112778U Pending JPS6221545U (ja) 1985-07-23 1985-07-23

Country Status (1)

Country Link
JP (1) JPS6221545U (ja)

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