JPS62213266A - Pattern formation - Google Patents
Pattern formationInfo
- Publication number
- JPS62213266A JPS62213266A JP5506286A JP5506286A JPS62213266A JP S62213266 A JPS62213266 A JP S62213266A JP 5506286 A JP5506286 A JP 5506286A JP 5506286 A JP5506286 A JP 5506286A JP S62213266 A JPS62213266 A JP S62213266A
- Authority
- JP
- Japan
- Prior art keywords
- film
- films
- unnecessary
- stencil
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007261 regionalization Effects 0.000 title claims description 3
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000001681 protective effect Effects 0.000 claims abstract description 13
- 238000001704 evaporation Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 238000009833 condensation Methods 0.000 claims 1
- 230000005494 condensation Effects 0.000 claims 1
- 238000001020 plasma etching Methods 0.000 abstract description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052593 corundum Inorganic materials 0.000 abstract description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract description 4
- 238000001755 magnetron sputter deposition Methods 0.000 abstract description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- 238000005566 electron beam evaporation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 101150079463 NBL1 gene Proteins 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000009834 vaporization Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- JHJNPOSPVGRIAN-SFHVURJKSA-N n-[3-[(1s)-1-[[6-(3,4-dimethoxyphenyl)pyrazin-2-yl]amino]ethyl]phenyl]-5-methylpyridine-3-carboxamide Chemical compound C1=C(OC)C(OC)=CC=C1C1=CN=CC(N[C@@H](C)C=2C=C(NC(=O)C=3C=C(C)C=NC=3)C=CC=2)=N1 JHJNPOSPVGRIAN-SFHVURJKSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000021110 pickles Nutrition 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000527 sonication Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は歩留りの良い超伝導素子などの半導体amの製
造における多躇配線用パタン形成法に圓する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming patterns for multi-hesitant interconnections in the manufacture of semiconductors such as superconducting elements with high yield.
(従来技術及び発明が解決しようとする問題虐)従来、
リフトオフ法によるパタン形成においては、ステンシル
(パタン形成用のマスク)の側壁に付着する不要膜をで
きるだけ少なくするため第3図に示すようにステンシル
2にオーバーハング構造2aを形成し、かつ指向性の強
い、iai法(3はNI!方向を示す)で所望の114
を堆積する方法が用いられてきた。このような方法で形
成した躾では側壁に付着する不T1膜はあまり厚くない
ため、超呂波処理を中心とする不要膜除去法によって容
易に除去されていた。しかし指向性の強い蒸着法はすべ
ての材料に適用できるわけではなく、例えば非常にma
が轟く、かつ雰囲気中の不純物を膜中に取り込みやすい
NbヤNb化合物などの超電導材料や窒化物等膜形成時
に反応させて形成する膜の場合にはスパッタ法による成
膜が適している。ところで、スパッタ法による成膜にお
いては膜を堆積すべき基板に飛来する物質粒子は非常に
ランダムである口とがよく知られている。従ってたとえ
ステンシルにオーバーハング構造を形成しても不式な膜
が1常に厚くステンシルの11壁に付着し、超高波処理
技術をもってしても完全に取除くのは困難であった。(Prior art and problems to be solved by the invention) Conventionally,
In pattern formation using the lift-off method, an overhang structure 2a is formed on the stencil 2 as shown in FIG. 3, and a directional strong, the desired 114 in the iai method (3 indicates the NI! direction)
methods have been used to deposit Since the non-T1 film adhering to the sidewalls of the fibers formed by such a method is not very thick, it can be easily removed by unnecessary film removal methods such as ultra-fine treatment. However, highly directional vapor deposition methods cannot be applied to all materials;
In the case of a film formed by reacting during film formation, such as a superconducting material such as Nb or a Nb compound or a nitride, which generates a loud noise and easily incorporates impurities in the atmosphere into the film, sputtering is suitable for film formation. By the way, it is well known that in film formation by sputtering, the material particles that fly onto the substrate on which the film is to be deposited are extremely random. Therefore, even if an overhang structure is formed on the stencil, the irregular film always adheres thickly to the wall of the stencil, and it is difficult to completely remove it even with ultrahigh wave treatment technology.
第4図において〈イ)図はステンシル2をマスクとして
基板(図示せず)上に第1の配線1m21を形成した状
態を示す。この場合ステンシル2の肩部のとごろにはオ
ーバーハング2aが形成されているので、ステンシル2
の側壁には不要1121′が形成される。しかしてステ
ンシルをリフトオフした債では(ロ)図のように不要1
121’の部分はバリ22として残る。次に第1配置1
aM21に絶#R1123を形成した状態は(ハ)図に
示される。この絶縁膜23の上に第2の配@f1424
を形成した状態は(ニ)図に示される。しかしてバリ2
2のために、第1配線1121と第2の配[11124
とが短絡されてしまう。(ホ)図はパリの発生しない理
想的な場合を示すものである。In FIG. 4, (a) shows a state in which a first wiring 1m21 is formed on a substrate (not shown) using the stencil 2 as a mask. In this case, since an overhang 2a is formed around the shoulder of the stencil 2, the stencil 2
An unnecessary portion 1121' is formed on the side wall of. However, for bonds with lift-off stencils, unnecessary 1 is shown in (b) figure.
A portion 121' remains as a burr 22. Next, the first arrangement 1
The state in which the absolute #R1123 is formed on the aM21 is shown in Figure (c). On this insulating film 23, a second wiring @f1424
The state in which it has been formed is shown in Figure (d). However, Bali 2
2, the first wiring 1121 and the second wiring [11124
will be short-circuited. (e) The figure shows an ideal case in which Paris does not occur.
第5図は上下の配線層の間に介在した絶tillにスル
ホールを;9け、このスルホールに導1性材料を充填し
て、両配線層を接続する場合を示すもので、第3の配K
A@25上にステンシル2を形成した状態を(イ)図に
示す。次に第3の配線間25上にスルホール形成のため
の層間絶縁膜を形成した状態を(ロ)図に示す。ついで
ステンシル2をリフトオフした状態を(ハ)図に示す。Figure 5 shows the case where nine through holes are formed in the gap between the upper and lower wiring layers, and the through holes are filled with a conductive material to connect both wiring layers. K
Figure (A) shows the state in which the stencil 2 is formed on A@25. Next, a state in which an interlayer insulating film for forming through holes is formed on the third wiring gap 25 is shown in FIG. The state in which the stencil 2 is then lifted off is shown in FIG.
ついで第4の配線間28を形成した状態を(ニ)図に示
す。口のような状態ではスルホールに介在するパリ27
′のために、両配[11125と28とは隔離されて電
気的接続を行うことはできない。(ホ)図は理想的な状
態を示す。The state in which the fourth wiring gap 28 is then formed is shown in FIG. In the mouth-like state, Paris 27 is interposed in the through hole.
Because of this, both wirings [11125 and 28 are isolated and cannot be electrically connected. (e) The figure shows an ideal state.
このようにパタン上に口のような不Illが残っている
と、不要1122の^さはステンシルの高さに等しく通
常数百0−〜1μ−程度に達するから、第4図の場合は
!IIIIJ絶縁が不完全になり配線間のショー1〜が
起こり、第5図の場合は、1!権配線相豆の接続が行わ
れない。そこで、従来、スパッタ法で堆積した躾をリフ
トオフする際にはリフトオフする前にいったん堆積した
膜をエツチングし、側壁に付着している不要膜を完全に
除去するか、または非常に漣くして超音波処理による除
去を容易にする方法がとられていた。しかし堆積した膜
厚が1100n以上になると、側壁にf1看する不¥I
IIの厚さも厚くなり、不要膜をエツチングしている間
に堆積膜厚し減少してしまう。この堆積膜厚の減少を補
うために、あらかじめ堆積膜の厚さをエツチングで減少
する分厚く堆積する方法も試みられたが、膜ストレスの
強い材料では堆積膜厚が数百nlを超えると、レジスト
ステンシル自体が躾のストレスに耐えられず剥離するた
め、膜厚の増加には限界があった。If a mouth-like irregularity remains on the pattern like this, the height of the unnecessary 1122 is equal to the height of the stencil and usually reaches several hundred 0-1μ-, so in the case of Fig. 4! IIIJ insulation becomes incomplete and shows 1~ between the wires occur, and in the case of Figure 5, 1! The power line connection is not made. Conventionally, when lifting off a layer deposited by sputtering, the deposited film is etched before lift-off to completely remove the unnecessary film adhering to the sidewalls, or the unnecessary film adhering to the sidewalls is either completely removed or Methods have been used to facilitate removal by sonication. However, when the thickness of the deposited film exceeds 1100n, the sidewalls are exposed to f1.
The thickness of II also increases, and the thickness of the deposited film decreases while etching the unnecessary film. In order to compensate for this decrease in the deposited film thickness, attempts have been made to reduce the thickness of the deposited film in advance by etching it to make it thicker. There was a limit to the increase in film thickness because the stencil itself could not withstand the stress of training and would peel off.
以上説明したようにスパッタ法を用いて#I積した膜を
従来の超音波のみを用いる方法や、エツチングで不ff
1Qを除去する方法では、ステンシル側壁の不要膜を完
全には除去することができず、従って配線間のショート
や断線による歩留りの低下が避けられない大巾があった
。As explained above, the #I layered film using the sputtering method can be removed by conventional methods using only ultrasonic waves or by etching.
In the method of removing 1Q, unnecessary films on the side walls of the stencil cannot be completely removed, and therefore, there is a large amount of unavoidable reduction in yield due to short circuits and disconnections between wiring lines.
(問題点を解決するための手段)
本発明は上記の大海を改善するために提案されたもので
堆積膜の膜厚を減少させることなく、完全に側壁に付着
した不要膜を除去する方法を提供する口とを目的とする
。(Means for Solving the Problems) The present invention has been proposed in order to improve the above-mentioned problems, and provides a method for completely removing unnecessary films attached to side walls without reducing the thickness of the deposited film. The purpose is to provide mouths.
上記の目的を達成するため、本発明は基板上にあらかじ
めステンシルを形成する工程と、前記の基板上に所望の
材料の第1の躾を堆積する工程と、前記の膜の堆積後、
リフトオフ前に凝縮性が強く、かつエツチングにより除
去可能な材料を、指向性の良い蒸発方法で堆積して保:
!膜を形成する工程と、前記の保護膜をマスクとして、
前記の第1の膜の形成時に、前記のステンシルの側壁に
付着した不要膜を除去する工程と、ついでリフトオフを
行う工程とを具備することを特徴とするパタン形成法を
発明の要旨とするものである。To achieve the above object, the present invention comprises the steps of pre-forming a stencil on a substrate, depositing a first layer of a desired material on said substrate, and after depositing said film.
Deposit and preserve highly condensable and etching-removable materials using a well-directed evaporation method before lift-off:
! A step of forming a film, and using the above-mentioned protective film as a mask,
The gist of the invention is a pattern forming method characterized by comprising a step of removing an unnecessary film adhering to the side wall of the stencil when forming the first film, and then a step of performing lift-off. It is.
本発明の特徴は、側壁の不要膜の除去に先立ち、エツブ
ーングされては困る堆積膜の上に指向性の良い蒸器法で
エツチングに対する保”31A@fli@I、、しかる
後に不要膜をエツチングすることにある。The feature of the present invention is that, prior to removing the unnecessary film on the sidewall, the deposited film, which should not be etched, is protected against etching using a vaporization method with good directionality.Then, the unnecessary film is etched. There is a particular thing.
この場合、保fallは、不要膜を除去するエツチング
に対して必ずしも耐性を持つ必要はなく、側壁の不要膜
のエツチングが終了するまでなくならないだけの厚さが
あれば良い。また保1lllとして用いる材料は堆積膜
と同じあるいは異なるエラチャン1〜にJ:リリフ]・
オフ前に完全に除去される必要がある。本発明によると
、従来の技術とは異なり熔(a膜を損うことなく側壁の
不要膜を完全に除去できるから多閾配線の歩留りを向上
させることができる。In this case, the protective fall does not necessarily have to be resistant to etching to remove the unnecessary film, but only needs to be thick enough to not disappear until the unnecessary film on the side wall is etched. In addition, the material used for the protective film may be the same as or different from the deposited film.
Must be completely removed before turning off. According to the present invention, unlike the conventional technology, unnecessary films on the sidewalls can be completely removed without damaging the a-film, so the yield of multi-threshold wiring can be improved.
次に本発明の詳細な説明する。なお実施例は一つの例示
であって、本発明の精神を逸脱しない範囲で、種々の変
更あるいは改良を行いうろことは云うまでもない。Next, the present invention will be explained in detail. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.
〔実施例1〕 第1図は本発明の第1の実施例を示す。[Example 1] FIG. 1 shows a first embodiment of the invention.
(イ)図は基板31上に、肩部にオーバーハングを有す
るステンシル32を形成し、ついで基板31上にNb唐
33(1)、Al10333(21,Nbl1!33(
3)を形成する。(A) In the figure, a stencil 32 with an overhang on the shoulder is formed on a substrate 31, and then Nb 33 (1), Al10333 (21, Nbl1!33 (21), Nbl1!33 (
3) Form.
34はこの場合ステンシル32の両側壁に形成された不
11134を示す。ついで上記の集積層の上にエツチン
グ時の3i保:1!1136を形成した状態を示す。34 indicates a hole 11134 formed on both side walls of the stencil 32 in this case. Next, a state in which a 3i bond:1!1136 during etching is formed on the above-mentioned integrated layer is shown.
(ロ)図はエツチングにより側壁に付着した不要膜をリ
フトオフした状態を示す。次にステンシル32上に堆積
した膜及びNbl1!3上のS1保護膜を除去すること
により、雄板31上にNil/AI、 03′NbFR
を形成する口とができる。(B) The figure shows the state in which the unnecessary film attached to the side wall has been lifted off by etching. Next, by removing the film deposited on the stencil 32 and the S1 protective film on Nbl1!3, Nil/AI and 03'NbFR are deposited on the male plate 31.
A mouth can be formed.
こCでNb、’AI□03.’Nb積磨膜33(1)、
+21. (3)はIIcマグネトロンスパッタ法で
、Si保護膜3Gは電子ビーム蒸む法で堆積した。Nh
、、’AI□03.’Nb堆積膜の厚さが400no+
の時、−側壁の不式膜厚34は150niであった。こ
の場合Si保護膜厚3Gを200+vとし、平行平板型
反応性イオンエツチング(旧[)装置内で15Paのl
Icl3+CH4で2分間エツチングしたとごろ側壁に
付着した不要$34は完全に除去され、かつSiに保護
されて必要なNb/Al2O3/Nb膜はエツチングさ
れなかった。この11(i)残ったSi躾を6[4の反
応性イオンエツブング法(旧[)を用いて除去してリフ
トオフし、超伝導トンネル接合を形成し1iil不要膜
を超畠波処理のみで除去した場合、(iii)3i保護
IIなしでエツチングしてそれぞれ形成したトンネル接
合の特性と比較した、その結果本発明の方法で形成した
接合では測定した100接合中1個のショートもなく、
リーク7Ii流も小さかったのに対し、超音波のみを使
用した場合には100接合中20接合がショート、Si
保護膜なしでエツチングした場合には100接合中12
接合がショートする一方、大半の接合にリーク電流の増
大が認められた。これは、不要膜除去の際、必要なNb
、’AI□03 /Nb積IIm!の上部Nb膜を同時
にエツチングして膜厚を岬<シすぎたためである。この
膜厚の減少するための上部のNbを40001にし、全
体のi!Fjを6000■にしたところステンシルが基
板から剥離してバターニングできなかった。このように
本発明の方法では、絶縁不良を起すことなく歩留り良(
Nb/^1□03z’Nb接合が形成できた。At this C, Nb, 'AI□03. 'Nb laminated film 33 (1),
+21. (3) was deposited by the IIc magnetron sputtering method, and the Si protective film 3G was deposited by the electron beam vaporization method. Nh
,,'AI□03. 'The thickness of the Nb deposited film is 400no+
At the time, the informal film thickness 34 of the − sidewall was 150 ni. In this case, the Si protective film thickness 3G was set to 200+V, and the etching process was performed at 15 Pa in a parallel plate type reactive ion etching (former) apparatus.
After etching with Icl3+CH4 for 2 minutes, the unnecessary $34 adhering to the side wall was completely removed, and the necessary Nb/Al2O3/Nb film was not etched as it was protected by Si. This 11(i) remaining Si layer is removed and lifted off using the reactive ion etching method (formerly [) of 6[4], a superconducting tunnel junction is formed, and the 1iil unnecessary film is removed only by ultrasonic processing. When removed, (iii) the characteristics were compared with those of tunnel junctions formed by etching without 3i protection II, and as a result, the junctions formed by the method of the present invention did not have one short circuit out of 100 junctions measured.
The leakage 7Ii current was also small, whereas when only ultrasonic waves were used, 20 out of 100 connections were shorted, and Si
When etched without a protective film, 12 out of 100 connections were achieved.
While the junctions were short-circuited, an increase in leakage current was observed in most of the junctions. This is because the necessary Nb is removed when removing unnecessary films.
, 'AI□03 /Nb product IIm! This is because the upper Nb film was etched at the same time, making the film too thick. To reduce this film thickness, the upper Nb is set to 40001, and the total i! When Fj was set to 6000 ■, the stencil peeled off from the substrate and patterning could not be performed. In this way, the method of the present invention achieves a good yield without causing insulation defects.
A Nb/^1□03z'Nb junction was formed.
〔実施例2〕 第2図は本発明の第2の実施例を示す。[Example 2] FIG. 2 shows a second embodiment of the invention.
(イ)図はSio241根上に、予めNb配線@42を
形成する。ついで配線層42上に肩部にオーバーハング
を有するスルーホールを形成するためのレジストステン
レス43を形成した後、5i02堆積■44を形成する
。この場合、ステンシル43の側壁にはバリ45が形成
される。ついで、口のバリ45を取除く際のエツチング
から、S!02IIを保護するためのPd47を堆積し
た状態を示す。(ロ)図はエツチングによって、ステン
シル43の側壁に付着したバリ45を除去した状態を示
す。ついで、ステンシル43上のSiO□躾44. P
d1147と、閾間絶1i11144上のI’d膜47
を除去することによって、スルホールを有する層間絶縁
■が形成される。(ハ)図はこの状態を示す。なお■閤
絶縁@44上に上部配線[48を形成する。この状態は
(ニ)因に示される。(a) In the figure, Nb wiring @42 is formed in advance on the root of Sio241. Next, a resist stainless steel 43 is formed on the wiring layer 42 to form a through hole having an overhang at the shoulder portion, and then a 5i02 deposit 44 is formed. In this case, burrs 45 are formed on the side walls of the stencil 43. Next, from etching when removing the burr 45 from the mouth, S! This shows the state in which Pd47 is deposited to protect 02II. (B) The figure shows a state in which the burr 45 attached to the side wall of the stencil 43 has been removed by etching. Next, SiO □ discipline 44. on the stencil 43. P
d1147 and I'd film 47 on threshold interval 1i11144
By removing this, interlayer insulation (2) having through holes is formed. (c) The figure shows this state. Note that ① an upper wiring [48] is formed on the insulation @44. This condition is shown in cause (d).
リフトオフ法で形成した5i02コンタク1〜ホールを
介して(Sin2@厚300nl)gl厚400nmの
上部Nb配線と下部Nb配線のコンタクl〜の歩留りを
調べるため(+vt本発明によるPdを保!!膜を使用
して151’aの02F、反応性イオンエツチング法(
RIE)で不要膜を除去してそののち酸洗いでPdを除
去しリフトオフした場合、(V)超音波のみでリフトオ
フした場合(vi)保:1!膜なしでエツチングした場
合について比較したその結果、(iv)の本発明の方法
によれば100%の歩留りであったが、(v)の従来法
では95%と歩留りが低下し、さらにコンタクトしてい
る場合でも超伝導臨界電流の低下がみられた。これは不
要膜によって上部Nb電極が切断され、あるいは非常に
傳くなったためである。また(vi)では歩留りは10
096であったものの両電圧間の耐圧の低下がみられた
。口のように、本発明の方法によるとスパッタの5i0
2をリフトオフしてスルーホールを形成した場合、歩留
り良くコンタクトを形成できる。実施例2においてPd
の代わりにAuを用い、保yL膜としての役割終了後酸
洗浄ではな(、Arのスパッタエッチで除去した場合、
Pdの代わりにSiOを用い、C[4系ガスの反応性エ
ツチングで除去した場合も同様の効果が冑られた。In order to investigate the yield of 5i02 contact 1 ~ hole formed by lift-off method (Sin 2 @ thickness 300 nl) of contact 1 ~ of upper Nb wiring and lower Nb wiring with GL thickness of 400 nm (+vt Pd retention!! film according to the present invention). 02F of 151'a using reactive ion etching method (
RIE) to remove unnecessary film and then pickle to remove Pd and perform lift-off, (V) lift-off using only ultrasound (vi) Preservation: 1! As a result of comparing the case of etching without a film, the method (iv) of the present invention had a yield of 100%, but the conventional method (v) had a yield of 95%, and the yield was lowered to 95%. A decrease in superconducting critical current was observed even when This is because the upper Nb electrode was cut off by the unnecessary film or became very loose. Also, in (vi) the yield is 10
096, but a decrease in breakdown voltage between both voltages was observed. According to the method of the present invention, the spatter 5i0
When through-holes are formed by lifting off 2, contacts can be formed with a high yield. In Example 2, Pd
When Au is used instead of , and it is removed by Ar sputter etching instead of acid cleaning after the role as a YL film is completed,
A similar effect was obtained when SiO was used instead of Pd and removed by reactive etching with C[4-based gas.
(発明の効果)
以上説明したように、本発明の方法によるとステンシル
側壁に付着した不a膜を完全に除去してリフトオフ可能
であるため、従来不W膜によって引起されていた金属配
線間のショートや配線の断線を除さ、歩留り良く超電導
トンネル接合に代表される多■配線構造やコンタクトを
形成できる利点がある。(Effects of the Invention) As explained above, according to the method of the present invention, it is possible to completely remove the non-Al film attached to the sidewall of the stencil and lift-off, so that it is possible to completely remove the non-Al film attached to the side wall of the stencil. It has the advantage of eliminating short-circuits and wire breaks, and can form multi-wiring structures and contacts, such as superconducting tunnel junctions, with high yield.
第1図は本発明方法の第1実施例、第2図は同上第2実
施例、第3図、第4図及び第5図は従来方法を示す。
1・・・・基板、2・・・・A−バーハング構造を有す
るステンシル、3・・・・蒸着粒子、4・・・・堆積す
べき膜、21・・・・第1の配線■、22・・・・lI
vに付着して形成された不9に膜、23・・・・間開絶
縁膜、24・・・・第2の配線−125・・・・第3の
配線請、26・・・・スルーホール形成のための圓間絶
It膜、21・・・・絶縁膜の不要膜、28・・・・第
4の配III、31・・・・基板、32・・・・オーバ
ーハング形状を持つステンシル、33・・・Nb/At
20:、 、’Nb1i、 34−・−ステ>シL@M
ニ付着した不要膜、35・・・・不要膜、36・・・・
Si保″:!!膜、41・・・・5i(12基板、42
・・・・Nb配線@、43・・・・レジストステンシル
、44・・・・5i(l□堆積閤、45・・・・側壁に
付むした不要膜、41・・・・Pd保護膜、48・・・
・上部Nb1S[!線
第1 図
(イ)
(ロ)
カー°−s−課護履
第2図
(イ) (ロ)第3図FIG. 1 shows a first embodiment of the method of the present invention, FIG. 2 shows a second embodiment of the same, and FIGS. 3, 4, and 5 show a conventional method. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Stencil having A-bar hang structure, 3... Vapor deposition particles, 4... Film to be deposited, 21... First wiring ■, 22 ...lI
23...Gap insulating film, 24...Second wiring-125...Third wiring line, 26...Through A discontinuous It film for hole formation, 21... an unnecessary film of an insulating film, 28... a fourth wiring III, 31... a substrate, 32... having an overhang shape Stencil, 33...Nb/At
20:, ,'Nb1i, 34-・-ste>shiL@M
D attached unnecessary film, 35... unnecessary film, 36...
Si protection'':!!Film, 41...5i (12 substrates, 42
...Nb wiring@, 43...Resist stencil, 44...5i (l□deposition layer, 45...Unnecessary film attached to side wall, 41...Pd protective film, 48...
・Upper Nb1S [! Line Figure 1 (A) (B) Car°-s- Section Figure 2 (A) (B) Figure 3
Claims (2)
、前記の基板上に所望の材料の第1の膜を堆積する工程
と、前記の膜の堆積後、リフトオフ前に凝縮性が強く、
かつエッチングにより除去可能な材料を、指向性の良い
蒸発方法で堆積して保護膜を形成する工程と、前記の保
護膜をマスクとして、前記の第1の膜の形成時に、前記
のステンシルの側壁に付着した不要膜を除去する工程と
、ついでリフトオフを行う工程とを具備することを特徴
とするパタン形成法。(1) forming a stencil on a substrate in advance; depositing a first film of a desired material on the substrate; and after depositing the film and before lift-off, the film has a strong condensation property;
and forming a protective film by depositing a material that can be removed by etching using a well-directed evaporation method; A pattern forming method comprising the steps of removing an unnecessary film attached to the substrate, and then performing lift-off.
いずれかを用いることを特徴とする特許請求の範囲第1
項記載のパタン形成法。(2) Claim 1, characterized in that any one of Si, Au, Pd, and SiO is used as the material for the protective film.
Pattern formation method described in section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5506286A JPS62213266A (en) | 1986-03-14 | 1986-03-14 | Pattern formation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5506286A JPS62213266A (en) | 1986-03-14 | 1986-03-14 | Pattern formation |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62213266A true JPS62213266A (en) | 1987-09-19 |
Family
ID=12988198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5506286A Pending JPS62213266A (en) | 1986-03-14 | 1986-03-14 | Pattern formation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62213266A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015119014A (en) * | 2013-12-18 | 2015-06-25 | 日亜化学工業株式会社 | Semiconductor light-emitting element and method for forming electrode of the same |
US11972902B2 (en) | 2021-09-28 | 2024-04-30 | Tdk Corporation | Electronic apparatus with a metal terminal having portions of differing elasticity |
-
1986
- 1986-03-14 JP JP5506286A patent/JPS62213266A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015119014A (en) * | 2013-12-18 | 2015-06-25 | 日亜化学工業株式会社 | Semiconductor light-emitting element and method for forming electrode of the same |
US11972902B2 (en) | 2021-09-28 | 2024-04-30 | Tdk Corporation | Electronic apparatus with a metal terminal having portions of differing elasticity |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0191438A (en) | Manufacture of semiconductor device | |
JPS5828736B2 (en) | How to form a flat thin film | |
JPS62213266A (en) | Pattern formation | |
JP2985326B2 (en) | Method for manufacturing semiconductor device | |
JPS63250155A (en) | Manufacture of semiconductor device | |
JPH02246246A (en) | Manufacture of semiconductor device | |
JP2936680B2 (en) | Method for manufacturing semiconductor device | |
JP2991388B2 (en) | Method for manufacturing semiconductor device | |
JPH0290623A (en) | Manufacture of semiconductor device | |
KR100487476B1 (en) | Method of forming semiconductor devices and semiconductor devices formed thereby | |
JPH01238043A (en) | Method of forming wiring | |
JPS62245650A (en) | Manufacture of multilayer interconnection structure | |
JPS61141157A (en) | Manufacture of semiconductor element | |
JPS61154048A (en) | Wiring and manufacture thereof | |
JPH05326507A (en) | Forming method of electrode or wiring | |
JPH02140927A (en) | Manufacture of semiconductor device | |
JPS5815253A (en) | Manufacture of electrode of semiconductor device | |
JPS59189687A (en) | Manufacture of josephson junction element | |
JPS6083350A (en) | Manufacture of integrated circuit | |
JPS62249451A (en) | Manufacture of multilayer interconnection structure | |
JPH0193146A (en) | Formation of multilayer interconnection | |
JPH0319222A (en) | Manufacture of semiconductor device | |
JPH0350828A (en) | Method of forming gold wiring | |
JPH0451530A (en) | Manufacture of semiconductor integrated circuit device | |
JPH04264733A (en) | Formation of bump base film for integrated circuit device |