JP2936680B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2936680B2
JP2936680B2 JP2241768A JP24176890A JP2936680B2 JP 2936680 B2 JP2936680 B2 JP 2936680B2 JP 2241768 A JP2241768 A JP 2241768A JP 24176890 A JP24176890 A JP 24176890A JP 2936680 B2 JP2936680 B2 JP 2936680B2
Authority
JP
Japan
Prior art keywords
film
gold
forming
gold bump
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2241768A
Other languages
Japanese (ja)
Other versions
JPH04120734A (en
Inventor
猛 福田
義文 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2241768A priority Critical patent/JP2936680B2/en
Publication of JPH04120734A publication Critical patent/JPH04120734A/en
Application granted granted Critical
Publication of JP2936680B2 publication Critical patent/JP2936680B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔概要〕 金バンプの形成方法に関し, 工数の削減と費用の低減を目的とし, 半導体基板上に形成された金属膜に接触する金バンプ
を形成するに際し,該金属膜表面に形成された自然酸化
膜からなる変質層を除去し,つづいて該半導体基板を外
気に触れさせることなく不活性雰囲気のもとにあるめっ
き装置に搬送し,金めっきを行うことにより該金属膜に
接触する金バンプを形成する工程を含む半導体装置の製
造方法により構成する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] A method of forming a gold bump is described in connection with a method of forming a gold bump in contact with a metal film formed on a semiconductor substrate. The altered layer consisting of a natural oxide film formed on the surface is removed, and then the semiconductor substrate is transferred to a plating apparatus under an inert atmosphere without being exposed to the outside air, and is subjected to gold plating. It is constituted by a method of manufacturing a semiconductor device including a step of forming a gold bump in contact with a film.

〔産業上の利用分野〕[Industrial applications]

本発明は半導体装置の製造方法に係り,特に,金バン
プの形成方法に関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gold bump.

LSIの高集積化の進展に伴い,金バンプ形成をチップ
上で行い,TAB(テープ・オートメーテッド・ボンディン
グ)方式により実装を完成する流れが大きくなってきて
いる。
With the progress of high integration of LSIs, the flow of forming gold bumps on a chip and completing mounting by TAB (Tape Automated Bonding) method is increasing.

TABリードは金バンプと外部端子を接続するもので,LS
I製造工程において,金バンプを安価にかつ歩留りよく
形成することが課題となっている。
The TAB lead connects the gold bump to the external terminal.
In the manufacturing process, it is an issue to form gold bumps at low cost and with good yield.

〔従来の技術〕[Conventional technology]

第3図(a)〜(c)は従来の金バンプの形成を示す
工程順断面図であり,以下,これらの図を参照しながら
従来の金バンプの形成方法を説明する。
3 (a) to 3 (c) are cross-sectional views in the order of steps showing the formation of a conventional gold bump. Hereinafter, a conventional method of forming a gold bump will be described with reference to these drawings.

第3図(a)参照 Si基板1上にAl配線2が形成され,Al配線2を保護す
る絶縁膜3が形成されている。絶縁膜3にAl配線2を外
部に接続するための開孔を形成し,全面にTi(チタン)
をスパッタしてTi膜4を形成し,つづいてPd(パラジウ
ム)をスパッタしてPd膜12を形成する。ついで,レジス
トを被着してそれをパターニングして金バンプを形成す
るための開孔を持つレジストマスク5を形成する。
Referring to FIG. 3 (a), an Al wiring 2 is formed on a Si substrate 1, and an insulating film 3 for protecting the Al wiring 2 is formed. An opening is formed in the insulating film 3 for connecting the Al wiring 2 to the outside, and Ti (titanium) is formed on the entire surface.
Is sputtered to form a Ti film 4, and then Pd (palladium) is sputtered to form a Pd film 12. Next, a resist is deposited and patterned to form a resist mask 5 having openings for forming gold bumps.

第3図(b)参照 その開孔からPd膜12の上にAu(金)めっきして金めっ
き層6を形成する。
Referring to FIG. 3B, Au (gold) plating is performed on the Pd film 12 from the opening to form a gold plating layer 6.

第3図(c)参照 レジストマスク5を除去し,さらに金めっき層6をマ
スクにしてPd膜12とTi膜4をエッチングし,金バンプ6a
を完成する。
Referring to FIG. 3C, the resist mask 5 is removed, and the Pd film 12 and the Ti film 4 are etched using the gold plating layer 6 as a mask.
To complete.

TiはAlとAuとの直接接触を避けるためのバリアメタル
としての役割をもつが,Tiは表面の活性度が大きいので
酸化膜が成長し易く,金めっき工程に入る以前に表面に
変質層が形成され,その上に金バンプを形成するとバン
プ剥がれを生じてしまう。このバンプ剥がれを回避する
ため,PdをTiに連続して成長している。
Ti has a role as a barrier metal to avoid direct contact between Al and Au, but Ti has a high surface activity, so it is easy for oxide films to grow, and an altered layer is formed on the surface before entering the gold plating process. When a gold bump is formed thereon, the bump is peeled off. To avoid this bump peeling, Pd is continuously grown on Ti.

一方,Pdの存在,及びPd膜を形成するための工程の増
加は製造コストを大きくする不利を生じる。
On the other hand, the presence of Pd and the increase in the number of steps for forming the Pd film cause a disadvantage that the manufacturing cost is increased.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

本発明は,Ti膜の上に直接密度性のよい金バンプを形
成する方法を提供し,Pd膜を中間に形成する従来法に比
べて費用削減を図ることを目的とする。
An object of the present invention is to provide a method of forming a gold bump having a high density directly on a Ti film, and to reduce the cost as compared with the conventional method of forming a Pd film in the middle.

〔課題を解決するための手段〕[Means for solving the problem]

上記課題は,半導体基板1上に形成された金属膜4に
接触する金バンプ6aを形成するに際し,該金属膜4表面
に形成された自然酸化膜からなる変質層を除去し,つづ
いて該半導体基板1を外気に触れさせることなく不活性
雰囲気のもとにあるめっき装置8に搬送し,金めっきを
行うことにより該金属膜4に接触する金バンプ6aを形成
する工程を含む半導体装置の製造方法によって解決され
る。
The object is to form a gold bump 6a in contact with the metal film 4 formed on the semiconductor substrate 1 by removing an altered layer made of a natural oxide film formed on the surface of the metal film 4, Manufacturing of a semiconductor device including a step of transporting the substrate 1 to a plating apparatus 8 under an inert atmosphere without being exposed to the outside air, and forming a gold bump 6a in contact with the metal film 4 by performing gold plating. Solved by the method.

〔作用〕[Action]

通常,金バンプ6a形成のためのレジストマスクを形成
する段階で,例えばTiのような金属膜4の表面に変質層
の形成は避けられないのであるが,本発明ではこの変質
層を除去し,つづいて外気に触れさせることなく半導体
基板を不活性雰囲気のもとにあるめっき装置8に搬送す
る。このようにすれば,変質層除去後,金メッキ開始ま
でに変質層が形成されることがない。
Usually, at the stage of forming a resist mask for forming the gold bump 6a, it is unavoidable to form an altered layer on the surface of the metal film 4 such as Ti, but in the present invention, this altered layer is removed. Subsequently, the semiconductor substrate is transported to the plating apparatus 8 under an inert atmosphere without being exposed to the outside air. In this way, the altered layer is not formed after the altered layer is removed and before the gold plating is started.

したがって,従来のようなPd膜の形成は不要となり,
費用削減が図れる。
Therefore, the conventional formation of a Pd film becomes unnecessary,
Cost reduction can be achieved.

〔実施例〕〔Example〕

第1図(a)〜(c)は本発明の金バンプの形成を示
す工程順断面図であり,1はSi基板,2はAl配線,3は絶縁
膜,4はTi膜,5はレジストマスク,6は金めっき層,6aは金
バンプを表す。第2図は金バンプの形成を行う製造装置
を説明するための模式図であり,7はエッチング室,8はめ
っき室,9は搬送機構,10a,10b,11a,11bはバルブを表す。
1 (a) to 1 (c) are cross-sectional views in the order of steps showing the formation of a gold bump according to the present invention. The mask, 6 indicates a gold plating layer, and 6a indicates a gold bump. FIG. 2 is a schematic diagram for explaining a manufacturing apparatus for forming a gold bump, wherein 7 denotes an etching chamber, 8 denotes a plating chamber, 9 denotes a transport mechanism, and 10a, 10b, 11a, and 11b denote valves.

以下,これらの図を参照しながら,本発明の実施例に
ついて説明する。
Hereinafter, embodiments of the present invention will be described with reference to these drawings.

Si基板1上にAl配線2が形成され,Al配線2を保護す
る絶縁膜3が形成されている。絶縁膜3にAl配線2を外
部に接続するための開孔を形成し,全面にTi(チタン)
をスパッタし,厚さが約0.5μmのTi膜4を形成する。
An Al wiring 2 is formed on a Si substrate 1, and an insulating film 3 for protecting the Al wiring 2 is formed. An opening is formed in the insulating film 3 for connecting the Al wiring 2 to the outside, and Ti (titanium) is formed on the entire surface.
Is sputtered to form a Ti film 4 having a thickness of about 0.5 μm.

ついで,レジストを被着してそれをパターニングして
金バンプを形成するための開孔を持つレジストマスク5
を形成する。この時,Ti膜4表面は酸化して極く薄い変
質層が形成される(第1図(a))。
Next, a resist mask 5 having an opening for depositing a resist and patterning the resist to form a gold bump is formed.
To form At this time, the surface of the Ti film 4 is oxidized to form an extremely thin altered layer (FIG. 1A).

このシリコン基板をエッチング室7内に配置し,RFエ
ッチによりTi膜4表面に残るレジストの残滓と変質層を
除去する。
This silicon substrate is placed in the etching chamber 7, and the resist residue and the altered layer remaining on the surface of the Ti film 4 are removed by RF etching.

その後バルブ10b,11bを開いてシリコン基板を搬送機
構9によりエッチング室7からめっき室8へ搬送する。
搬送機構9のある部屋及びめっき室8は,窒素を流して
不活性雰囲気にしている(第2図)。
Thereafter, the valves 10b and 11b are opened, and the silicon substrate is transferred from the etching chamber 7 to the plating chamber 8 by the transfer mechanism 9.
The room in which the transfer mechanism 9 is located and the plating room 8 are set to an inert atmosphere by flowing nitrogen (FIG. 2).

窒素雰囲気のもとに金めっきを行い,Ti膜4上に厚さ2
0〜30μmの金めっき層6を形成する(第1図
(b))。
Perform gold plating in a nitrogen atmosphere and apply a thickness of 2
A gold plating layer 6 having a thickness of 0 to 30 μm is formed (FIG. 1B).

バルブ11aを開けて半導体基板を取り出し,レジスト
マスク5を除去し,つづいて金めっき層6をマスクにし
てTi膜4をエッチングして除去し,金バンプ6aを形成す
る(第1図(c))。
The semiconductor substrate is taken out by opening the valve 11a, the resist mask 5 is removed, and then the Ti film 4 is removed by etching using the gold plating layer 6 as a mask to form a gold bump 6a (FIG. 1 (c)). ).

なお,Ti膜4表面の変質層は,スパッタ装置を用いて
逆スパッタを行うことにより除去することもできる。
The altered layer on the surface of the Ti film 4 can also be removed by performing reverse sputtering using a sputtering device.

〔発明の効果〕〔The invention's effect〕

以上説明したように,本発明によれば,従来中間に形
成されていたPd膜が不要となり,費用低減が達成され
る。
As described above, according to the present invention, the Pd film conventionally formed in the middle becomes unnecessary, and the cost can be reduced.

本発明はLSIの費用低減と歩留り向上に寄与するもの
である。
The present invention contributes to LSI cost reduction and yield improvement.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(c)は本発明の金バンプの形成を示す
工程順断面図, 第2図は金バンプ形成を行う製造装置を説明するための
模式図, 第3図(a)〜(c)は従来の金バンプの形成を示す工
程順断面図, である。 図において, 1は半導体基板であってSi基板, 2はAl配線, 3は絶縁膜, 4は金属膜であってTi膜, 5はレジストマスク, 6は金めっき層, 6aは金バンプ, 7はエッチング室, 8はめっき室, 9は搬送機構, 10a,10b,11a,11bはバルブ, 12はPd膜 を表す。
1 (a) to 1 (c) are sectional views in the order of steps showing the formation of a gold bump according to the present invention, FIG. 2 is a schematic view for explaining a manufacturing apparatus for forming a gold bump, and FIG. 3 (a). FIGS. 1C to 1C are cross-sectional views in the order of steps showing the formation of a conventional gold bump. In the figure, 1 is a semiconductor substrate and a Si substrate, 2 is an Al wiring, 3 is an insulating film, 4 is a metal film and a Ti film, 5 is a resist mask, 6 is a gold plating layer, 6a is a gold bump, 7 Denotes an etching chamber, 8 denotes a plating chamber, 9 denotes a transport mechanism, 10a, 10b, 11a, 11b denotes a valve, and 12 denotes a Pd film.

フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 Continuation of front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板(1)上に形成された金属膜
(4)に接触する金バンプ(6a)を形成するに際し,該
金属膜(4)表面に形成された自然酸化膜からなる変質
層を除去し,つづいて該半導体基板(1)を外気に触れ
させることなく不活性雰囲気のもとにあるめっき装置
(8)に搬送し,金めっきを行うことにより該金属膜
(4)に接触する金バンプ(6a)を形成する工程を含む
ことを特徴とする半導体装置の製造方法。
When forming a gold bump (6a) in contact with a metal film (4) formed on a semiconductor substrate (1), an alteration comprising a natural oxide film formed on the surface of the metal film (4). The layer is removed, and then the semiconductor substrate (1) is transferred to a plating apparatus (8) under an inert atmosphere without being exposed to the outside air, and the metal film (4) is plated by gold plating. A method for manufacturing a semiconductor device, comprising a step of forming a gold bump (6a) to be in contact with the semiconductor device.
JP2241768A 1990-09-12 1990-09-12 Method for manufacturing semiconductor device Expired - Lifetime JP2936680B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2241768A JP2936680B2 (en) 1990-09-12 1990-09-12 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2241768A JP2936680B2 (en) 1990-09-12 1990-09-12 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH04120734A JPH04120734A (en) 1992-04-21
JP2936680B2 true JP2936680B2 (en) 1999-08-23

Family

ID=17079239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2241768A Expired - Lifetime JP2936680B2 (en) 1990-09-12 1990-09-12 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2936680B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950004464A (en) * 1993-07-15 1995-02-18 김광호 Manufacturing method of chip bump
JPH10209210A (en) 1997-01-20 1998-08-07 Sharp Corp Semiconductor device, its manufacture, and its inspection method
JP2011055033A (en) * 2009-08-31 2011-03-17 Kyocera Kinseki Corp Piezoelectric oscillator

Also Published As

Publication number Publication date
JPH04120734A (en) 1992-04-21

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