JPH02205323A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02205323A JPH02205323A JP2507289A JP2507289A JPH02205323A JP H02205323 A JPH02205323 A JP H02205323A JP 2507289 A JP2507289 A JP 2507289A JP 2507289 A JP2507289 A JP 2507289A JP H02205323 A JPH02205323 A JP H02205323A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- silicon nitride
- film
- bonding pad
- reliability
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 claims 4
- 229910000838 Al alloy Inorganic materials 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 11
- 239000011521 glass Substances 0.000 abstract description 4
- 150000002739 metals Chemical class 0.000 abstract description 3
- 239000002245 particle Substances 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 230000006837 decompression Effects 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に外部電極
取り出し用のボンディングパッドに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a bonding pad for taking out an external electrode.
〔従来の技術］
従来微細化された半導体装置の配線方法は、第２図の如
く、例＾ば半導体素子が形成された半導体基板２１上の
第１、第２のフィールド酸化膜２３．２４を介して不純
物層２２等からコンタクトボールが開孔され、例えばＡ
ｌ２−３ｉの様なＡ９合金Ｉｔ＠２５を０．５〜１．０
ｕｍスパックしてからマイグレーション特性の向上とフ
ォトリソ工程のハレーション防止の為に、例えば窒化チ
タン膜２６を０．３〜１．０μｍ程度スパッタする。次
に前記積層膜を同時にドライエツチングしてから、パシ
ベーションｌ！２７として気相反応のシリコン酸化膜や
シリコン窒化膜を析出させ、外部電極取り出し用のボン
ディングパッド部２８を形成する為、パシベーション膜
２７の一部をウェット及びドライエツチングする。この
時窒化チタン膜２６の表面は気相反応や、０．プラズマ
等によるレジスト剥離の際に反応し、後工程で行なうワ
イヤーボンディングの密着性や信頼性が劣る、従って、
ＣＦ ４に０□を添加したプラズマエッチングにより、
パッド部の窒化チタン膜２６を完全除去している。[Prior Art] Conventionally, as shown in FIG. 2, a wiring method for a miniaturized semiconductor device involves, for example, connecting first and second field oxide films 23 and 24 on a semiconductor substrate 21 on which a semiconductor element is formed. A contact ball is opened from the impurity layer 22 etc. through the hole, for example, A.
A9 alloy It@25 like l2-3i from 0.5 to 1.0
After um spacking, a titanium nitride film 26 is sputtered to a thickness of about 0.3 to 1.0 μm, for example, in order to improve migration characteristics and prevent halation in the photolithography process. Next, the laminated film is dry etched at the same time, and then passivation l! As step 27, a silicon oxide film or a silicon nitride film is deposited by vapor phase reaction, and a part of the passivation film 27 is wet and dry etched to form a bonding pad section 28 for taking out the external electrode. At this time, the surface of the titanium nitride film 26 undergoes a gas phase reaction or a 0. It reacts during resist removal using plasma, etc., and the adhesion and reliability of wire bonding performed in the subsequent process are poor.
By plasma etching with 0□ added to CF4,
The titanium nitride film 26 on the pad portion is completely removed.
〔発明が解決しようとする課題１
しかしながら従来技術では、パッド部２８の窒化チタン
膜２６を除去する為プラズマエツチングを行なっている
が、エツチング形状が等方性で、窒化チタン膜２６はチ
タンをＮ２中でスパッタして形成するが、ウェハー内に
均一に成膜するのは難しく、よって除去には過剰のオー
バーエツチングが必要な為、パシベーション膜の下に大
きなサイドエッチが入ってしまい、コンタミネーション
トラップになったり、半導体装置チップを高温でグイボ
ンディングする時にパッド部周辺の雪庇となったパシベ
ーション膜からのクラック、パーティクルが発生し、組
み立て、実装の歩留りや信頼性上の問題となっている。[Problem to be Solved by the Invention 1] However, in the prior art, plasma etching is performed to remove the titanium nitride film 26 on the pad portion 28, but the etched shape is isotropic and the titanium nitride film 26 is It is formed by sputtering inside the passivation film, but it is difficult to form a film uniformly on the wafer, so excessive overetching is required to remove it, resulting in large side etches under the passivation film, creating a contamination trap. When semiconductor device chips are bonded at high temperatures, cracks and particles are generated from the passivation film around the pads, causing problems in assembly and mounting yields and reliability.
しかるに本発明は、かかる課題を解決するものであり、
その目的とするところは、組み立て実装の歩留りや信頼
性を向上した微細半導体装置を安定供給することにある
。However, the present invention solves these problems,
The aim is to stably supply microscopic semiconductor devices with improved assembly and mounting yields and reliability.
［課題を解決するための手段］
本発明の半導体装置の製造方法は、Ａｆｆ合金薄膜上に
高融点金属またはその化合物からなる導電膜を積層した
配線構造を有する半導体装置の製造方法に於いて、ボン
ディングパッド部の該導電膜をエツチング除去する工程
と、パシベーション膜を積層する工程と、前記除去領域
よりも狭い範囲でパシベーション膜を開孔する工程を具
備したことを特徴とする。[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes the following steps: The present invention is characterized by comprising the steps of etching away the conductive film in the bonding pad portion, stacking a passivation film, and opening a hole in the passivation film in an area narrower than the region to be removed.
［実 施 例１
以下本発明の実施例に於ける工程を、第１図に基づいて
詳細に説明する。[Example 1] Hereinafter, steps in an example of the present invention will be explained in detail based on FIG.
サブミクロンルールの集積回路製造に於いて、トランジ
スタや抵抗等の半導体素子が形成された半導体基板１１
上の第１２第２のフィールド酸化膜１３．１４を介して
不純物層１２からコンタクトホールが開孔されており、
配線用のＡｆｆ合金１５を約１．０ｕｍ、連続して窒化
チタン膜Ｉ６を約０．０５μｍスパッタした後、フォト
レジストをマスクにして、前記積層ｌｌ＊１５．１６を
ＣＩ２ ｘ系ガスでドライエツチングして同時パターニ
ングした後、ボンディングパッド部１８をポジフォトレ
ジスト１９でパターニングした（第１図（ａ））、続い
てＣ□Ｆ８と０２を混入した平行平板のドライエツチャ
ーを使用し０．５ｔｏｒｒ、２５０Ｗで等方性エツチン
グした。この時ポジフォトレジスト１９はオーバー露光
し、更に窒化チタン１１１１６はオーバーエツチングし
たので、窒化チタン膜１６はパッドのガラスマスク寸法
より２．５μｍ程度大きく除去しである（第１図（ｂ）
）、その後レジスト１９を剥ぎ、パシベーション膜１７
としてＳ ｉＨａとＮＨ，を減圧中でプラズマ気相成長
させたシリコン窒化膜を約１．０ｕｍ積層し、続いてボ
ンディングパッド部１８を開孔する為、前記シリコン窒
化膜を、ＮＦ、と０２ガスを用いてドライエツチングし
た。この時フォト用のガラスマスクとレジストは、窒化
チタン膜１６を除去した時と同じものを使用したが、ア
ンダー露光することによって、開孔寸法はガラスマスク
寸法より０．５ｕｍ程度狭くなっている（第１図（Ｃ）
）、この結果耐湿性の低い窒化チタン膜は、シリコン窒
化膜で完全に覆われると共に、従来の様なシリコン窒化
膜の雪庇は形成されず、クラック、パーティクルの発生
は起こらなくなった。In the production of integrated circuits under the submicron rule, a semiconductor substrate 11 on which semiconductor elements such as transistors and resistors are formed.
A contact hole is opened from the impurity layer 12 through the upper 12th second field oxide film 13.14,
After sputtering Aff alloy 15 for wiring to a thickness of about 1.0 um and successively sputtering a titanium nitride film I6 of about 0.05 μm, using a photoresist as a mask, the laminated layer 11*15.16 was dry etched with CI2 x-based gas. After simultaneous patterning, the bonding pad portion 18 was patterned with a positive photoresist 19 (FIG. 1(a)), and then a parallel plate dry etcher containing C□F8 and 02 was used to pattern the bonding pad at 0.5 torr. , and isotropically etched at 250W. At this time, the positive photoresist 19 was overexposed and the titanium nitride 11116 was overetched, so the titanium nitride film 16 was removed approximately 2.5 μm larger than the pad glass mask dimension (Fig. 1(b)).
), then the resist 19 is removed and the passivation film 17 is removed.
A silicon nitride film of approximately 1.0 um is deposited by plasma vapor deposition of SiHa and NH under reduced pressure.Next, in order to open the bonding pad portion 18, the silicon nitride film is deposited with NF and 02 gas. Dry etching was performed using At this time, the same glass mask and resist for photo were used as those used when removing the titanium nitride film 16, but due to underexposure, the aperture size was about 0.5 um narrower than the glass mask size ( Figure 1 (C)
), as a result, the titanium nitride film, which has low moisture resistance, was completely covered with the silicon nitride film, and unlike the conventional silicon nitride film, the cornice of the silicon nitride film was not formed, and cracks and particles no longer occurred.
この様にしてなる半導体装置の組み立て、実装工程の歩
留りは向上し、信頼性上の問題も改善された。The yield of the assembly and mounting process of semiconductor devices made in this manner has been improved, and reliability problems have also been improved.
尚、窒化チタン膜のエツチングは、ＣＦ、、Ｃ，Ｆ、に
限らずＣＨＦ、やＮＦ、もしくは０□、Ｈｅ等との混合
ガスを用いたドライエツチャーでも可能である。この他
の実施例として、へ２合金の２層配線構造や、パシベー
ション構造がシリコン窒化膜の下にＰＳＧ膜やＮＳＣ膜
をストレス緩和の為に積層しである半導体装置のボンデ
ィングパッド部にも本発明を適用したが、前記と同様な
改善が見られた。Note that the etching of the titanium nitride film is not limited to CF, C, or F, but may also be performed using a dry etcher using CHF, NF, or a mixed gas with 0□, He, or the like. Other examples include a two-layer wiring structure made of H2 alloy, and a passivation structure in which a PSG film or NSC film is laminated under a silicon nitride film to relieve stress. When the invention was applied, the same improvement as described above was observed.
又、ヒロック、マイグレーション防止膜として窒化チタ
ン膜を用いたが、これはフォトリソ工程でのハレーショ
ン防止も兼ねている為で有り、これに限らずＭｏ、Ｗ、
Ｔ ｉ、Ｔａの様な高融点金属やそのシリサイド等の導
電材でも応用できる。In addition, a titanium nitride film was used as a hillock and migration prevention film, but this also serves to prevent halation in the photolithography process.
It can also be applied to conductive materials such as high melting point metals such as Ti and Ta and their silicides.
又Ａ２合金配線としては、Ａｌ２−５ｉに限らずＴｉ、
Ｃｕ、Ｐｔ等やこれらの混合物を含む２元、３元系の合
金でも良く、更に配線の下に、バリア金属を敷いた場合
にも適用できる。In addition, A2 alloy wiring is not limited to Al2-5i, but also Ti,
A binary or ternary alloy containing Cu, Pt, etc. or a mixture thereof may be used, and a barrier metal may be placed under the wiring.
以上の如く本発明によれば、ＡＩ２合金上に異種金属等
を積層した配線構造であって、ボンディングパッド部の
該異種金属をパシベーション膜の開孔寸法より広く除去
することにより、積層金属配線の特性を損なうこともな
く、組み立て、実装歩留り、信頼性を向上する効果があ
り、微細半導体装置の実用化と安定供給が可能となる。As described above, according to the present invention, in the wiring structure in which dissimilar metals, etc. are laminated on the AI2 alloy, the dissimilar metal in the bonding pad portion is removed wider than the opening size of the passivation film, thereby forming the laminated metal wiring. It has the effect of improving assembly, mounting yield, and reliability without impairing characteristics, making it possible to commercialize and stably supply microscopic semiconductor devices.
１１． １２、 ｌ ３． １４゜ ｌ ５． １６． １７゜ １８、 ｌ ９ ・ ２ ｌ ・ ２２ ・ ２３ ・ ２４ ・ ２５ ・ ２６ ・ ２７ ・ ２８ ・ ・半導体基板 ・不純物層 ・第１のフィールド酸化膜 ・第２のフィールド酸化膜 ・Ａｊ２合金膜 ・窒化チタン膜 ・パシベーション膜 ・ボンディングパッド部 ・ポジレジスト 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 上 柳 雅 誉（他１名）11. 12, l 3. 14° l 5. 16. 17° 18, l 9 ・ 2 l・ 22・ 23・ 24・ 25・ 26・ 27・ 28・ ・Semiconductor substrate ・Impurity layer ・First field oxide film ・Second field oxide film ・Aj2 alloy film ・Titanium nitride film ・Passivation film ・Bonding pad part ・Positive resist that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Homare Kamiyanagi (1 other person)
第１図（ａ）〜（Ｃ）は１本発明の一実施例による配線
形成工程を示す概略断面図である。
第２図は、従来の配線形成工程を示す概略断面図である
。FIGS. 1A to 1C are schematic cross-sectional views showing a wiring forming process according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view showing a conventional wiring forming process.
Claims (1)
導電膜を積層した配線構造を有する半導体装置の製造方
法に於いて、ボンディングパッド部の該導電膜をエッチ
ング除去する工程と、パシベーション膜を積層する工程
と、前記除去領域よりも狭い範囲でパシベーション膜を
開孔する工程を具備したことを特徴とする半導体装置の
製造方法。A method for manufacturing a semiconductor device having a wiring structure in which a conductive film made of a high-melting point metal or a compound thereof is laminated on an Al alloy thin film includes a step of etching away the conductive film at a bonding pad portion and laminating a passivation film. A method for manufacturing a semiconductor device, comprising: a step of opening a hole in a passivation film in an area narrower than the removed region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2507289A JPH02205323A (en) | 1989-02-03 | 1989-02-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2507289A JPH02205323A (en) | 1989-02-03 | 1989-02-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02205323A true JPH02205323A (en) | 1990-08-15 |
Family
ID=12155723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2507289A Pending JPH02205323A (en) | 1989-02-03 | 1989-02-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02205323A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07230995A (en) * | 1994-02-17 | 1995-08-29 | Nec Corp | Semiconductor device |
| JP2006303452A (en) * | 2005-03-25 | 2006-11-02 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2007103593A (en) * | 2005-10-03 | 2007-04-19 | Seiko Instruments Inc | Semiconductor device and its manufacturing method |
| JP2010251537A (en) * | 2009-04-16 | 2010-11-04 | Renesas Electronics Corp | Semiconductor integrated circuit device, and method of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891651A (en) * | 1981-11-26 | 1983-05-31 | Seiko Epson Corp | Semiconductor device |
| JPS63285939A (en) * | 1987-05-18 | 1988-11-22 | Nec Corp | Semiconductor device |
| JPS6410648A (en) * | 1987-06-22 | 1989-01-13 | Standard Microsyst Smc | Method of multilayer metallization for integrated circuit |
-
1989
- 1989-02-03 JP JP2507289A patent/JPH02205323A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5891651A (en) * | 1981-11-26 | 1983-05-31 | Seiko Epson Corp | Semiconductor device |
| JPS63285939A (en) * | 1987-05-18 | 1988-11-22 | Nec Corp | Semiconductor device |
| JPS6410648A (en) * | 1987-06-22 | 1989-01-13 | Standard Microsyst Smc | Method of multilayer metallization for integrated circuit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07230995A (en) * | 1994-02-17 | 1995-08-29 | Nec Corp | Semiconductor device |
| JP2006303452A (en) * | 2005-03-25 | 2006-11-02 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2007103593A (en) * | 2005-10-03 | 2007-04-19 | Seiko Instruments Inc | Semiconductor device and its manufacturing method |
| JP2010251537A (en) * | 2009-04-16 | 2010-11-04 | Renesas Electronics Corp | Semiconductor integrated circuit device, and method of manufacturing the same |
| US9048200B2 (en) | 2009-04-16 | 2015-06-02 | Renesas Electronics Corporation | Semiconductor integrated circuit device and method of manufacturing same |
| CN104835795A (en) * | 2009-04-16 | 2015-08-12 | 瑞萨电子株式会社 | Semiconductor device |
| US9536821B2 (en) | 2009-04-16 | 2017-01-03 | Renesas Electronics Corporation | Semiconductor integrated circuit device having protective split at peripheral area of bonding pad and method of manufacturing same |
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