JP2015119014A - Semiconductor light-emitting element and method for forming electrode of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element and a method for forming an electrode of the element, in which insulating property of an insulating film is improved, a short circuit of an electrode can be prevented and reliability can be increased.SOLUTION: The method for forming an electrode of a semiconductor light-emitting element 1 includes: a step of forming an n-side electrode layer 11 and a p-side electrode layer 12, in which at least one electrode layer is formed by a lift-off process using a resist as a mask; a step of forming an insulating film 20, in which the insulating film 20 is formed by forming an insulating resin by a spin coat process on the whole surface over the n-side electrode layer 11 and the p-side electrode layer 12; and a step of forming an n-pad electrode 31 and a p-pad electrode 32, in which a pad electrode electrically connected to at least one electrode layer is formed on the other electrode layer, different from the one electrode layer, via the insulating film 20.

Description

  The present invention relates to a semiconductor light emitting device and an electrode forming method thereof, and more particularly to a semiconductor light emitting device mounted face down and an electrode forming method thereof.

  Flip chip mounting is a mounting method in which the substrate side facing the electrode surface of the semiconductor light emitting element is the main light extraction surface, and is also referred to as face-down mounting (see Patent Document 1). A semiconductor light emitting device used for face-down mounting has a structure having both a p-pad electrode and an n-pad electrode on a surface facing an element substrate, and is mounted on an external mounting substrate with the electrode surface facing down. The face-down mounting is performed by using metal bumps or an adhesive layer made of an alloy.

  If the electrodes of the semiconductor light emitting element are formed by, for example, a lift-off method, an electrode having a predetermined shape can be formed by removing the mask. Patent Documents 2 and 3 describe a technique for forming a protective layer (insulating film) of a semiconductor light emitting element by a CVD method or a spin coating method.

JP 2005-19939 A JP 2006-73815 A JP 2011-100755

  In recent years, an n-pad electrode electrically connected to an n-type semiconductor layer via an insulating film is provided on a p-type semiconductor layer, and both the p-pad electrode and the n-pad electrode are disposed on the p-type semiconductor layer. Various semiconductor light emitting devices have been proposed. The semiconductor light emitting device having such a structure can improve the face-down mounting property by eliminating the step between the p pad electrode and the n pad electrode. Further, by increasing the bonding area between the p-pad electrode and n-pad electrode and the mounting surface, the bonding strength / accuracy and heat dissipation can be improved.

  However, in the case of the electrode structure proposed in recent years, for example, if a gap or a crack occurs in an insulating film formed when an n-pad electrode is provided on a p-side electrode, The electrode and the n-side electrode may be short-circuited. Even if it is not short-circuited immediately after forming the electrode, driving the semiconductor light-emitting element may connect the p-side electrode and the n-side electrode through a gap between the insulating films and the like, thereby causing a short circuit. Therefore, it is required to improve the insulating property of the insulating film provided between the p-side electrode and the n-side electrode.

  The present invention has been made in view of the above-described problems, and can improve the insulation of an insulating film, prevent a short circuit of an electrode, and improve the reliability of a semiconductor light emitting element and an electrode forming method thereof It is an issue to provide.

  In order to solve the above problems, an electrode forming method for a semiconductor light emitting device according to the present invention includes a step of preparing a wafer having a first semiconductor layer and a second semiconductor layer, and a first region on the first semiconductor layer. Forming one electrode and forming a second electrode on the second semiconductor layer provided in another region on the first semiconductor layer; and on the first electrode and the second electrode, Forming an insulating film having a first opening for exposing a surface of the first electrode and a second opening for exposing a surface of the second electrode; and forming the first opening in a region on the insulating film through the first opening. Forming a first pad electrode electrically connected to one electrode and forming a second pad electrode electrically connected to the second electrode through the second opening in another region on the insulating film; The first electrode and the front In the step of forming the second electrode, at least one of the first electrode and the second electrode is formed by a lift-off method using a resist as a mask, and in the step of forming the insulating film, the first electrode In the step of forming the insulating film by forming an insulating resin on the entire surface of the second electrode by spin coating, and forming the first pad electrode and the second pad electrode, at least the one electrode A pad electrode electrically connected to the other electrode is formed on the other electrode different from the one electrode through the insulating film.

  In order to solve the above problems, a semiconductor light emitting device according to the present invention includes a semiconductor structure including a first semiconductor layer and a second semiconductor layer provided in a region on the first semiconductor layer; A semiconductor light emitting device comprising: a first electrode provided in another region on the first semiconductor layer; and a second electrode provided on the second semiconductor layer, wherein the first electrode and the second electrode An insulating film made of resin, provided on the second electrode, having a first opening on the first electrode and having a second opening on the second electrode; and the first electrode through the first opening; A first pad electrode provided in a region on the second electrode and on the insulating film; and connected to the second electrode through the second opening; and on the first electrode and on the insulating film. A second pad electrode provided in another region, and a peripheral edge of the upper surface of the second electrode In a higher position than the upper end of the burr formed on, characterized in that a top surface of the insulating film.

According to the electrode formation method for a semiconductor light emitting device according to the present invention, even if the first electrode and the second electrode have burrs, the burrs are covered with the insulating film and the upper surface of the insulating film is flattened. Can prevent gaps and cracks from occurring. Therefore, the insulating property of the insulating film can be improved, the electrode can be prevented from being short-circuited, and the reliability of the semiconductor light-emitting element having the electrode structure can be improved.
In addition, since the upper surface of the insulating film is at a position higher than the upper end of the generated burr, the semiconductor light emitting device according to the present invention can prevent the insulating film from generating gaps or cracks. Therefore, the insulating property of the insulating film can be improved, the short circuit of the electrode can be prevented, and the reliability of the semiconductor light emitting element can be improved.

It is the top view which looked at the semiconductor light-emitting device concerning the embodiment of the present invention from the electrode surface side. It is a schematic diagram which shows the cross section in the AA arrow of FIG. It is a schematic diagram which shows the cross section in the BB line arrow of FIG. FIG. 3 is an enlarged view of a region indicated by X in FIG. 2. It is a top view (the 1) in the manufacturing process of the semiconductor light-emitting device which concerns on embodiment of this invention. It is a top view in the manufacturing process of the semiconductor light-emitting device concerning the embodiment of the present invention (the 2). It is a top view (the 3) in the manufacturing process of the semiconductor light-emitting device which concerns on embodiment of this invention. 8A is a cross-sectional view of the end portion of the resist, FIG. 8B is a cross-sectional view of the electrode material laminated on the resist, and FIG. 8C is a cross-sectional view of the end portion of the electrode layer. It is typical sectional drawing which shows the formation procedure of the collar part of a resist. It is a top view (the 5) in the manufacturing process of the semiconductor light-emitting device concerning embodiment of this invention. It is a top view (the 6) in the manufacturing process of the semiconductor light-emitting device based on embodiment of this invention. 12A is a sectional view of an insulating layer formed on the electrode layer by the method of the comparative example, and FIG. 12B is a sectional view of the insulating layer formed on the electrode layer by the method of the embodiment of the present invention. It is sectional drawing.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out a semiconductor light emitting device and an electrode forming method thereof according to the present invention will be described in detail with reference to drawings showing some specific examples. Note that the size, positional relationship, and the like of the members shown in each drawing may be exaggerated for clarity of explanation. Furthermore, in the following description, the same names and symbols indicate the same or the same members in principle, and detailed description will be omitted as appropriate.

  First, the configuration of the semiconductor light emitting device 1 will be described with reference to FIGS. As shown in FIG. 1, the shape of the semiconductor light emitting element 1 is a rectangle when viewed from the electrode surface side. As shown in FIG. 2, the semiconductor light emitting device 1 includes a substrate 2, a semiconductor structure 3, an n-side electrode layer (first electrode) 11, a p-side electrode layer (second electrode) 12, and insulation. The film 20, an n pad electrode (first pad electrode) 31, a p pad electrode (second pad electrode) 32, a second insulating film 40, and translucent conductive films 51 and 52 are mainly provided. ing. In FIGS. 2 to 4, hatching indicating a cross section is not described in reference numerals 2, 4, 5, 6, and 452 for easy understanding.

  The semiconductor light emitting element 1 is an element that extracts light from the substrate 2 side to the outside, and is mounted face down using an alloy as an adhesive layer. Hereinafter, the configuration of each unit will be sequentially described in detail.

(Substrate 2)
As the material of the substrate 2, a material suitable when, for example, a gallium nitride compound semiconductor is used for the semiconductor structure 3 is used. Examples of such a substrate material include sapphire, spinel, SiC, Si, ZnO, and GaN single crystal. In particular, it is preferable to use a sapphire substrate in order to form gallium nitride with good crystallinity with high productivity. As shown in FIG. 2, the substrate 2 may have irregularities formed on the surface (surface on the electrode side) on which the semiconductor structure 3 is laminated. The unevenness can scatter or diffract light from the semiconductor structure 3 to increase light extraction efficiency.

(Semiconductor structure 3)
The semiconductor structure 3 is formed on the substrate 2, and an n-type semiconductor layer (first semiconductor layer) 4, an active layer 5, and a p-type semiconductor layer (second semiconductor layer) 6 are stacked in this order. Yes. The semiconductor structure 3 is formed with a recess 7 and a peripheral portion 8 having a step with respect to the upper surface. The concave portion 7 has a shape of a groove extending in the lateral direction along the line AA in FIG. In the example shown in FIG. 1, two recesses 7 are formed. The peripheral portion 8 is disposed so as to surround a substantial light emitting portion of the semiconductor structure 3, and can be used as a margin for cutting out the semiconductor light emitting element from the large-sized wafer after the electrodes are formed. .

  In the course of the manufacturing process of the semiconductor light emitting device 1, the p-type semiconductor layer 6 and the active layer 5 are partially removed and the underlying n-type semiconductor layer 4 is exposed, whereby the recess 7 and the peripheral portion 8 are formed. It is formed. Therefore, the p-type semiconductor layer 6 is provided in a region on the n-type semiconductor layer 4 so as to surround the recess 7. An n-side electrode layer 11 is provided on another region on the n-type semiconductor layer 4, that is, on the bottom surface of the recess 7 via a light-transmitting conductive film 51. On the p-type semiconductor layer 6, the p-side electrode layer 12 is provided via the translucent conductive film 52 and the second insulating film 40.

  In the semiconductor structure 3, one or both of the n-type semiconductor layer 4 that is the first semiconductor layer and the p-type semiconductor layer 6 that is the second semiconductor layer are configured in a multilayer structure in which a plurality of semiconductor layers are stacked. You can also. The active layer 5 may be a single layer or a multilayer. For example, each of the n-type semiconductor layer 4 and the p-type semiconductor layer 6 can be composed of a plurality of layers corresponding to necessary functions such as a contact layer and a clad layer, and realize light emission characteristics according to applications. Can do. For example, a configuration in which the first semiconductor layer is a p-type semiconductor layer and the second semiconductor layer is an n-type semiconductor layer may be employed.

(N-side electrode layer 11)
The n-side electrode layer 11 is an electrode layer made of a metal provided between the n-type semiconductor layer 4 and the n-pad electrode 31, and materials such as Ti, Rh, Pt, Ru, and Au can be used. The n-side electrode layer 11 is formed by stacking, for example, Ti, Rh, and Ti in order from the n-type semiconductor layer 4 side.
In the present embodiment, the n-side electrode layer 11 is electrically connected to the translucent conductive film 51 through the third through hole 43 of the second insulating film 40. As a modification, the n-side electrode layer 11 may be in direct contact with the n-type semiconductor layer 4 without the light-transmitting conductive film 51 interposed.

(P-side electrode layer 12)
The p-side electrode layer 12 is an electrode layer made of a metal provided between the p-type semiconductor layer 6 and the p-pad electrode 32. The material of the p-side electrode layer 12 is the same as that of the n-side electrode layer 11. The p-side electrode layer 12 is formed by stacking, for example, Ti, Rh, and Ti in order from the p-type semiconductor layer 6 side.
In the present embodiment, the p-side electrode layer 12 is electrically connected to the translucent conductive film 52 through the first through hole 41 of the second insulating film 40. The p-side electrode layer 12 has an anchor opening (through hole) 15. As a modification, the p-side electrode layer 12 may be in direct contact with the p-type semiconductor layer 6 without the light-transmitting conductive film 52 interposed.
When the p-side electrode layer 12 and the n-side electrode layer 11 are formed by a lift-off method, burrs may be formed at the peripheral edge of the upper surface. Here, it is assumed that the p-side electrode layer 12 has burrs 13 and 14 formed at the peripheral edge of the upper surface.

(Insulating film 20)
The insulating film 20 covers and protects the surface of the semiconductor light emitting element 1. The insulating film 20 is made of resin and is provided on the n-side electrode layer 11 and the p-side electrode layer 12. In the present embodiment, the upper surface of the insulating film 20 is provided at a position higher than the upper end of the burr 13 formed at the peripheral edge of the upper surface of the p-side electrode layer 12. The upper surface of the insulating film 20 is substantially flat, that is, the upper surface of the insulating film 20 is higher than the upper end of the burr 13 even on the p-side electrode layer 12 other than the vicinity of the burr 13. By doing so, since the insulating film 20 has a sufficient thickness, even if the p-side electrode layer 12 has burrs, no current leaks to the n-pad electrode 31 side. Even if the n-side electrode layer 11 has burrs, current does not leak to the p-pad electrode 32 side.

The material of the insulating film 20 is preferably a photosensitive fluororesin. If photosensitive, the insulating film can be formed into a desired pattern shape by photolithography. Further, when the fluororesin is cured, it becomes softer than when an oxide such as SiO ₂ is used as the insulating film, and gaps and cracks are less likely to occur.

As shown in FIG. 4, the thickness t ₂₀ of the insulating film 20 on the p-side electrode layer 12 is equal to or less than the film thickness t _{80 of the} resist used when forming the p-side electrode layer 12 (see FIG. 8A). Thus, it is preferable to form an insulating film. A thickness t ₂₀ of the insulating film 20 on the p-side electrode layer 12 can be set to 1 to 3 μm, for example. As a result, it is possible to provide a small-sized semiconductor light emitting element 1 that does not leak to the n pad electrode 31 side even if the p-side electrode layer 12 has the burr 13. As shown in FIG. 8 (a) ~ FIG 8 (c), typically, the thickness t ₁₃ of the burr 13 is less than that of the resist film thickness t _80, exceed the resist film thickness t ₈₀ even increased maximally There is no. Therefore, the thickness t ₂₀ of the insulating film 20 is equal to or resist film thickness t ₈₀ or less is considered to be sufficiently possible insulation.

<Through hole of insulating film 20>
The insulating film 20 has an n-side opening (first opening) 21 on the n-side electrode layer 11 and a p-side opening (second opening) 22 on the p-side electrode layer 12 (see FIG. 11).
The n-side opening 21 is made small as long as sufficient conduction can be obtained between the n-pad electrode 31 formed thereon and the n-side electrode layer 11 provided in the recess 7.
The p-side opening 22 is provided at least in a portion close to the n-side electrode layer 11 (portion close to the element center) at a position where the p-pad electrode 32 is formed. By forming at such a position, current diffusion in the semiconductor structure 3 can be prevented from being hindered. The p-side opening 22 is made as large as possible so that the contact resistance between the p-side electrode layer 12 and the p-pad electrode 32 becomes small. The size of the p-side opening 22 shown in FIG. 1 is an example, and may be less than half the size shown.

  In the present embodiment, the insulating film 20 is in contact with the translucent conductive film 52 through the anchor opening 15 of the p-side electrode layer 12 and the second through hole 42 of the second insulating film 40. Thereby, the translucent conductive film 52 prevents the insulating film 20 from being separated from the p-side electrode layer 12.

(N pad electrode 31)
The n pad electrode 31 is an electrode layer that becomes the outermost surface on the n side when the semiconductor light emitting element 1 is mounted. The n pad electrode 31 is electrically connected to the n side electrode layer 11 through the n side opening 21 of the insulating film 20, and is provided on the p side electrode layer 12 and in a region on the insulating film 20. That is, the n pad electrode 31 extends to the p-type semiconductor layer 6 through the insulating film 20 and is electrically connected to the n-type semiconductor layer 4.

  For example, the n pad electrode 31 is formed by stacking Ti, Pt, and Au sequentially from the n-side electrode layer 11 side. Alternatively, for example, the n pad electrode 31 may be formed by laminating Ti, Ni, and Au sequentially from the n-side electrode layer 11 side. As shown in FIG. 1, the n pad electrode 31 can have a vertically long rectangular shape in plan view. Further, as shown in FIGS. 1 and 3, a notch 33 may be formed in the n pad electrode 31. The notch 33 serves as a mark for the cathode (n-side electrode).

(P pad electrode 32)
The p pad electrode 32 is an electrode layer that is the outermost surface on the p side when the semiconductor light emitting element 1 is mounted. The p-pad electrode 32 is electrically connected to the p-side electrode layer 12 through the p-side opening 22 of the insulating film 20 and is also provided on the n-side electrode layer 11 and other regions on the insulating film 20. That is, the p pad electrode 32 extends to the n-type semiconductor layer 4 through the insulating film 20 and is electrically connected to the p-type semiconductor layer 6.

  For example, the p pad electrode 32 is formed by laminating Ti, Pt, Au, and the like in order from the p-side electrode layer 12 side. The p pad electrode 32 may have a stacked structure similar to that of the n pad electrode 31. As shown in FIG. 1, the p-pad electrode 32 can have a vertically long rectangular shape in plan view. In FIG. 1, for easy understanding, the p-pad electrode 32 and the n-pad electrode 31 existing in the foremost direction in the direction perpendicular to the paper surface are indicated by solid lines and denoted by reference numerals 7, 8, 21, 22, and the like. Regions are indicated by broken lines.

(Second insulating film 40)
In the present embodiment, as an example, the second insulating film 40 made of a multilayer film is further provided on the translucent conductive film 52. The second insulating film 40 is a light reflecting film for reducing light absorption by the p-side electrode layer 12 and improving light output. The second insulating film 40 has a light reflecting metal film 46 inside the multilayer film. Since the metal film 46 is entirely covered with an insulating material and is not electrically connected to the semiconductor structure 3 or the like, the metal film 46 will be described as a part of the second insulating film 40 here. Specifically, as shown in FIG. 4, the second insulating film 40 includes, for example, a base layer 44, a DBR (distributed Bragg reflector) 45, a metal film 46, and a cap from the translucent conductive film 52 side. Layer 47. Materials other than the metal film 46 are made of an insulating material.

The underlayer 44 is a layer that becomes the underlayer of the DBR 45. The underlayer 44 is made of an insulating film, and is particularly preferably made of an oxide film. Examples of the oxide film include Nb ₂ O ₅ , TiO ₂ , SiO ₂ , Al ₂ O ₃ , ZrO _{2 and the} like.

As shown in FIG. 4, the DBR 45 has a multilayer structure in which a plurality of sets of dielectrics each composed of a low refractive index layer 451 and a high refractive index layer 452 are stacked, and selectively transmits light having a predetermined wavelength. It is a reflection. Specifically, by stacking films having different refractive indexes alternately with an optical thickness of ¼ wavelength for the emission peak wavelength from the active layer 5, for example, a band centered on the emission peak wavelength. Can be reflected with high efficiency. The material is preferably selected from oxides or nitrides of at least one metal selected from the group consisting of Si, Ti, Zr, Nb, Ta, and Al.
When the DBR 45 is formed of an oxide film, the low refractive index layer 451 is formed of, for example, SiO ₂ . At this time, the high refractive index layer 452 is formed of, for example, Nb ₂ O ₅ , TiO ₂ , ZrO ₂ , Ta ₂ O ₅ or the like.

The metal film 46 is premised on that no current flows. The metal film 46 is formed of, for example, a highly reflective metal or alloy such as Al or Ag.
Since the metal film 46 is formed on the DBR 45, the light transmitted from the semiconductor structure 3 through the DBR 45 can be reflected. By combining the DBR 45 and the metal film 46, incident light can be efficiently reflected.

The cap layer 47 is a layer that covers and protects the metal film 46. The cap layer 47 is made of an oxide film such as SiO ₂ as with the base layer 44.

<Through hole of the second insulating film 40>
The second insulating film 40 has a first through hole 41, a second through hole 42, or a third through hole 43 inside each of a large number of through holes (see FIG. 7) of the metal film 46. . The number of second through holes 42 is one or more. In FIG. 8, as an example, through holes are provided in a substantially lattice shape of 8 rows and 10 columns, of which two upper left and lower left portions are second through holes 42, and the rest are first through holes 41. The number and arrangement of the first through holes 41 and the second through holes 42 are not limited to this. The third through-hole 43 is a groove along the longitudinal direction of the recess 7 and is formed narrower than the bottom surface of the recess 7.

  The average diameter of the second through-hole 42 is set to a predetermined range size. Here, the average diameter means the average value of the major axis and the minor axis when the planar shape of the second through-hole 42 is not circular, for example, when it is an ellipse, and when it is a square, the area of the square Is the diameter of a circle with the same area. When the average diameter is less than 5 μm, the resist pattern for etching is crushed and it is difficult to manufacture the second through hole 42. In addition, when the average diameter exceeds 15 μm, the second through hole 42 may inhibit current diffusion. Therefore, the average diameter of the second through holes 42 is preferably 5 μm or more and 15 μm or less. In the case of the first through hole 41 through which electricity flows, the average diameter is preferably 10 μm or more in order to improve current characteristics.

(Translucent conductive film 51)
The translucent conductive film 51 is provided on the n-type semiconductor layer 4 and functions as an ohmic electrode. The translucent conductive film 51 is formed of a thin film made of a metal, an alloy, or a conductive oxide. Examples of the conductive oxide (oxide semiconductor) include a conductive oxide film containing at least one element selected from the group consisting of zinc, indium, tin, gallium, and magnesium. Specifically, indium oxide containing tin (Indium Tin Oxide: ITO), ZnO, zinc oxide containing indium (Indium Zinc Oxide: IZO), zinc oxide containing gallium (Gallium-doped Zinc Oxide: GZO), In ₂ Examples thereof include O _{3 and} SnO ₂ . Particularly for conductive oxides, ITO is most preferable from the viewpoints of conductivity and translucency.

(Translucent conductive film 52)
The translucent conductive film 52 is provided on the p-type semiconductor layer 6 and functions as an ohmic electrode. The material of the translucent conductive film 52 is the same as that of the translucent conductive film 51. The translucent conductive film 52 is made of, for example, ITO. The translucency means a property of transmitting light emitted from the semiconductor light emitting element 1 to about 70% or more, about 80% or more, about 90% or more, or about 95% or more.

[Semiconductor light emitting device manufacturing process flow]
The manufacturing process of the semiconductor light emitting device 1 mainly includes a wafer preparation process, a pretreatment process, an electrode formation process, an insulating film formation process, a pad electrode formation process, and a wafer singulation process. . The wafer in the wafer singulation process is at least an n-side electrode layer (first electrode) 11, a p-side electrode layer (second electrode) 12, an insulating film 20, and an n-pad electrode (first pad electrode) 31. , P pad electrode (second pad electrode) 32 is formed.

  Hereinafter, as an example, description will be made with reference to FIGS. 5 to 7 (refer to FIGS. 1 to 4 as appropriate). 5 to 7 are schematic plan views showing the manufacturing process of the present invention, focusing on the separated semiconductor light emitting device 1 for the sake of explanation.

(Wafer preparation process)
First, a wafer having an n-type semiconductor layer (first semiconductor layer) 4 and a p-type semiconductor layer (second semiconductor layer) 6 is prepared. If there is an already manufactured wafer, it may be used. When manufacturing a wafer, specifically, an n-type semiconductor layer 4, an active layer 5, and a p-type semiconductor layer 6 are stacked in this order on a substrate 2 to form a semiconductor structure 3 (see FIG. 2). ). Then, a part of the semiconductor structure 3 is etched by, for example, RIE (Reactive Ion Etching reactive ion etching) to form the concave portion 7 and the peripheral portion 8 which are step portions of the semiconductor structure 3 as shown in FIG. .

(Pretreatment process)
The pretreatment step is a step performed before forming electrodes corresponding to the respective elements on the prepared wafer. In the electrode forming method according to the present invention, the pretreatment process is not particularly limited. Here, as an example, a light-transmitting conductive film or an insulating film is formed. In this case, as shown in FIG. 6, a translucent conductive film 51 is formed on the upper surface of the n-type semiconductor layer 4 exposed from the p-type semiconductor layer 6 in the recess 7, and the translucent film is formed on the upper surface of the p-type semiconductor layer 6. A conductive film 52 is formed.

  Next, as shown in FIG. 7, the second insulating film 40 having the first through hole 41, the second through hole 42, and the third through hole 43 is formed on the translucent conductive films 51 and 52.

(Electrode formation process)
In the electrode formation step, the n-side electrode layer 11 is formed in one region on the n-type semiconductor layer 4 and the p-side electrode layer is formed on the p-type semiconductor layer 6 provided in another region on the n-type semiconductor layer 4. 12 is a step of forming 12. In the electrode forming step, at least one of the n-side electrode layer 11 and the p-side electrode layer 12 is formed by a lift-off method using a resist as a mask. Here, both the n-side electrode layer 11 and the p-side electrode layer 12 are formed by a lift-off method.

  With reference to FIG. 8 (refer to FIG. 2 as appropriate), a method of forming the p-side electrode layer 12 on the second insulating film 40 as an underlayer by a lift-off method using a resist as a mask will be described as an example. The p-side electrode layer 12 can be formed by the following first step, second step, and third step.

In the first step, as shown in FIG. 8A, a resist 80 is formed on a part of the surface of the second insulating film 40 as a mask. Here, the film thickness of the resist and t _80. Here, the film thickness t ₈₀ is larger than the film thickness of the p-side electrode layer 12 to be formed.

  The resist 80 has a collar portion (overhang) 81 at its end edge. This collar part 81 is produced by a conventionally known method. For example, it can be manufactured by the following first-first process, first-second process, and first-third process using an inverted negative resist. Here, the reversal negative resist has a property that an exposed portion is dissolved by development. Also, the reversal negative resist has the property that, when the reversal process is performed before development, composition change (cross-linking) due to heat treatment occurs in the lighted part, and the lighted part remains by development. ing.

(First Step 1-1) As shown in FIG. 9A, generally, a resist 92 is formed on the surface of the substrate 91 (corresponding to the surface of the second insulating film 40 in this embodiment). Next, as shown in FIG. 9B, initial exposure is performed using a mask pattern 93 that masks a portion that does not leave the resist 92 after development. At this time, the exposure depth of the portion 94 to be exposed may be a depth that does not reach the lower surface of the resist 92. Thereby, the collar part 81 mentioned later can be formed.
(Step 1-2) As shown in FIG. 9C, an inversion step is performed. That is, reverse baking (reversal baking) is performed. As a result, the properties of the portion 94 exposed in step 1-1 are reversed. Specifically, the exposed portion 94 is given alkali resistance and ultraviolet light resistance by a crosslinking reaction by heat.
(Step 1-3) As shown in FIG. 9D, the entire surface is exposed. As a result, portions other than the region exposed in the initial exposure are exposed. Here, the region sandwiched between the broken lines of the resist 92 (immediately below the portion 94 exposed in the 1-1 process) is difficult to be exposed. Thereafter, as shown in FIG. 9 (e), the portion not exposed in the 1-1 step is removed by development, and the portion 94 exposed in the 1-1 step remains. At this time, the portion 94 immediately under the portion 94 exposed in the step 1-1 and reversed in the step 1-2 is not easily exposed to light, and the influence of the increase in solubility due to the overall exposure is small. For this reason, most of them remain after development, but the side surface 95 is slightly removed by wet etching with a developing solution, so that a flange 81 is formed.

  Here, the degree of reverse taper of the flange 81 depends on the exposure amount (exposure depth) in the 1-1 step, the development time in the 1-3 step, and the like. Note that the method of forming the collar portion 81 is not limited to this, and for example, it can be formed by changing the size of the mask and performing multiple exposures.

  Subsequent to the first step, in the second step, as shown in FIG. 8B, an electrode material such as Rh is used on the surface of the second insulating film 40 from above the resist 80 by, for example, sputtering. An electrode material layer 100 is formed. Thereby, the electrode material layer 100 adheres to the surface of the second insulating film 40 not covered with the resist 80. At this time, the electrode material layer 100 may not adhere to the side surface of the resist 80, but may partially adhere along the side surface.

  In the third step, for example, by immersing in a strong alkaline stripping solution, the resist 80 is stripped from the surface of the second insulating film 40 as shown in FIG. 8C, and the electrode material layer on the resist 80 together with the resist 80. 100 is also removed. Then, the electrode material layer 100 directly attached to the surface of the second insulating film 40 remains as the p-side electrode layer 12. At this time, the electrode material adhering to the side surface of the resist 80 remains as the burr 13 at the end of the p-side electrode layer 12 as it is.

For example, when the thickness of the resist 80 is about t ₈₀ = 2.5 μm in order to form the p-side electrode layer 12 having a thickness of several hundred nm, the thickness t _{13 of the} burr 13 measured from the upper surface of the p-side electrode layer 12. Was about 1 μm at maximum. If a resist in which the flange portion 81 is not formed is used, the electrode material easily adheres to the side surface of the resist 80, and a larger burr is likely to occur. On the other hand, when the resist 80 having the flange 81 is used, generation of burrs can be suppressed.

(Insulating film formation process)
The insulating film forming step is a step of forming the insulating film 20 on the n-side electrode layer 11 and the p-side electrode layer 12. In the insulating film forming step, first, the insulating film 20 is formed by forming an insulating resin on the entire surface of the n-side electrode layer 11 and the p-side electrode layer 12 by spin coating. Thereafter, an n-side opening 21 that exposes the surface of the n-side electrode layer 11 and a p-side opening 22 that exposes the surface of the p-side electrode layer 12 are provided in the insulating film 20.

  After at least one of the n-side electrode layer 11 and the p-side electrode layer 12 is formed by a lift-off method, burrs may be formed at the peripheral edge of the upper surface of the electrode layer. Therefore, in the insulating film forming step, it is preferable to form the insulating film 20 so that the upper surface of the insulating film 20 is higher than the upper end of the burr.

In the insulating film forming step, as shown in FIG. 4, the insulating film 20 has a thickness t ₂₀ of the insulating film 20 on the p-side electrode layer 12 equal to or less than the resist film thickness t ₈₀ (see FIG. 8A). 20 is preferably formed.

  When the n-side electrode layer 11 and the p-side electrode layer 12 shown in FIG. 10 are formed in the electrode forming step, the insulating film forming step starts from above the n-side electrode layer 11 and the p-side electrode layer 12. An insulating film 20 made of an insulating resin is formed on the entire surface (on the p-type semiconductor layer 6, the recess 7, and the periphery of the semiconductor structure 3) by spin coating.

  Thereby, the recess corresponding to the first through hole 41 on the surface of the p-side electrode layer 12 is filled with the insulating resin, and the unevenness on the surface of the p-side electrode layer 12 can be flattened. At this time, the insulating resin is stacked on the translucent conductive film 52 through the anchor opening 15 of the p-side electrode layer 12 and the second through hole 42 of the second insulating film 40 below the opening 15. It will be. Therefore, the unevenness in the anchor opening 15 is also flattened.

Then, by removing the insulating film 20 in the region including the plurality of first through holes 41 on the side (left side in FIG. 11) that becomes the p pad electrode 32 with the concave portion 7 interposed therebetween, as shown in FIG. 20, a p-side opening 22 is formed. In this embodiment, since the insulating film 20 is made of a photosensitive material, the insulating film can be easily formed into a desired pattern shape by exposure using a mask having a desired opening and immersion in a developer. can do. For example, when the insulating film 20 is composed of a negative resist similar to the resist used at the time of electrode formation, the portion to be removed may be exposed and immersed in the developer.
Similarly, the n-side opening 21 is formed by removing the insulating film 20 in a region including a part of the third through-hole 43 on the side that is to be the n-pad electrode 31 (right side in FIG. 11).

(Pad electrode formation process)
In the pad electrode forming step, an n pad electrode 31 that is electrically connected to the n side electrode layer 11 through the n side opening 21 is formed in one region on the insulating film 20, and through the p side opening 22 in another region on the insulating film 20. This is a step of forming a p-pad electrode 32 that is electrically connected to the p-side electrode layer 12.
In the pad electrode formation step, a pad electrode that is electrically connected to at least one electrode layer is formed on the other electrode layer with the insulating film 20 interposed therebetween. That is, as shown on the right side in FIG. 2, the n-pad electrode 31 that is electrically connected to the n-side electrode layer 11 is formed on the p-side electrode layer 12 so as to extend through the insulating film 20. Further, as shown on the left side in FIG. 2, a p-pad electrode 32 that is electrically connected to the p-side electrode layer 12 is formed on the n-side electrode layer 11 so as to extend through the insulating film 20.

  When the insulating film 20 shown in FIG. 11 is formed in the insulating film forming step, in this pad electrode forming step, an electrode material such as Ti, Pt, or Au is formed on the insulating film 20 by sputtering, for example. The n-pad electrode 31 and the p-pad electrode 32 are formed as shown in FIG.

(Wafer singulation process)
The wafer singulation step is a step of cutting out a large-sized wafer on which electrodes corresponding to each element are formed, into pieces of each element size. Note that the separated element is bonded to a mounting substrate or the like on the electrode surface side using an alloy as an adhesive layer. In addition, as a specific material of an adhesive layer, eutectic alloy films, such as an alloy which has Au and Sn as a main component, are mentioned, for example.

[Comparison of insulation properties of insulating films]
In order to form a part of the n-pad electrode 31 on the p-side electrode layer 12 or to form a part of the p-pad electrode 32 on the n-side electrode layer 11, the semiconductor light emitting element 1 An insulating film 20 is formed on the n-side electrode layer 11 and the p-side electrode layer 12. In the semiconductor light emitting device having such a three-dimensional electrode structure, when the p-side electrode layer 12 is formed by the lift-off method, burrs 13 may be generated in the vicinity of the region indicated by X in FIG. In the prior art, if a gap or crack occurs in the insulating film 20 around the burr 13, the p-side electrode layer 12 and the n-pad electrode 31 may be short-circuited. In addition, the p-side electrode layer 12 may have burrs 14 in the region indicated by Y in FIG. However, the electrode on the burr 14 of the p-side electrode layer 12 is the p-pad electrode 32, and there is no fear of a short circuit.
As in the case of the semiconductor light emitting device 1, the oxide film is formed by the sputtering method as to the effect of the embodiment in which the insulating resin is formed as the insulating film 20 on the n-side electrode layer 11 and the p-side electrode layer 12 by the spin coat method. This will be explained in comparison with

  As shown in FIG. 12A and FIG. 12B, a p-side electrode layer 120 is formed on a wafer 110 as a base. A part of the n-pad electrode 140 is formed on the p-side electrode layer 120 via the insulating film 130A or 130B. An insulating film 130A shown in FIG. 12A is an oxide film, and an insulating film 130B shown in FIG. 12B is an insulating resin film. In any case, an insulating film is formed on the surface of the wafer 110. The p-side electrode layer 120 and the n-pad electrode 140 are formed by a lift-off method using a general electrode material.

  When the insulating film 130A is formed by sputtering, the insulating film 130A adheres along the shape of the burr 121 on the burr 121 formed at the end of the p-side electrode layer 120, as shown in FIG. To do. Therefore, a cavity 131 is formed in the insulating film 130A along the shape of the burr 121, and the insulating film 130A cannot sufficiently cover the burr 121. If the electrode material of the n-pad electrode 140 wraps around the gap or crack generated in the cavity 131, the p-side electrode layer 120 and the n-pad electrode 140 are short-circuited and current leaks.

On the other hand, when the insulating film 130B is formed by spin coating so that the burr 121 generated at the end of the p-side electrode layer 120 is filled, the shape of the burr 121 is obtained as shown in FIG. Regardless, the upper surface of the insulating film 130B is flat. At this time, the thickness of the insulating film 130 </ b> B on the wafer 110 is larger than the thickness of the p-side electrode layer 120 including the burr 121. Therefore, no cavity is generated in the insulating film 130B, and the insulating film 130B can sufficiently cover the burr 121. Therefore, it is possible to prevent the p-side electrode layer 120 and the n pad electrode 140 from being short-circuited.
Even if the thickness of the p-side electrode layer 120 including the burr 121 is larger than the thickness of the insulating film 130B on the wafer 110, if the insulating film 130B is formed by spin coating, the p-side electrode layer 120 It is considered that it is possible to prevent the n pad electrode 140 from being short-circuited. Since the insulating resin used for the spin coating method is usually softer than SiO ₂ or the like formed by the sputtering method, the insulating film 130B formed by the spin coating method is relatively soft and hardly causes gaps or cracks. For this reason, even when the thickness of the p-side electrode layer 120 including the burr 121 is larger than the thickness of the insulating film 130 </ b> B, it is considered that no gap or crack is generated and a short circuit can be prevented. For example, when the material of the insulating film 130B is a fluorine-based resin, when cured, the material becomes softer than when an oxide such as SiO ₂ is used, and gaps and cracks are less likely to occur. Since gaps and cracks can be prevented, the p-side electrode layer 120 and the n-pad electrode 140 can be prevented from being short-circuited.

  Further, when the insulating film is formed by a spin coating method as in this embodiment, the upper surface of the insulating film can be flat even if the base has irregularities, unlike the sputtering method. Therefore, even in the case of an element having a structure with fine irregularities on the base, there is an effect that it is easy to form a conductive material for the pad electrode on the insulating film.

As described above, according to the semiconductor light emitting device 1 according to the present embodiment, even if the p-side electrode layer 12 has burrs, the p-side electrode layer 12 is insulated by the insulating film 20 covering the burrs. do not do. Further, even when the n-side electrode layer 11 has burrs, similarly, since it is insulated by the insulating film 20 covering the burrs, it does not leak to the p-pad electrode 32 side. Therefore, the reliability of the semiconductor light emitting element 1 can be improved.
Further, the semiconductor light emitting device 1 of the present embodiment has a structure in which both the n pad electrode 31 and the p pad electrode 32 are disposed on the p-type semiconductor layer 6, and is face-down compared to the conventional simple structure. Since the bonding area when mounted is large, the bonding strength / accuracy and heat dissipation can be improved.

  Each of the embodiments described above exemplifies a semiconductor light emitting element for embodying the technical idea of the present invention, and the present invention is not limited to these. Moreover, this specification does not specify the member shown by the claim as the member of each embodiment at all. The dimensions, materials, shapes, relative arrangements, and the like of the components described in each embodiment are not intended to limit the scope of the present invention only to specific examples unless otherwise specified. Only. Furthermore, each element constituting the present invention may be configured such that a plurality of elements are constituted by the same member and the plurality of elements are shared by one member, and conversely, the function of one member is constituted by a plurality of members. It can also be realized by sharing.

  For example, the second insulating film 40 is an electrode structure that reduces light absorption and improves light output by using a dielectric multilayer film or the like that reflects light. For example, DBR 45 or the like is not essential in the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor light-emitting device 2 Substrate 3 Semiconductor structure 4 N-type semiconductor layer (first semiconductor layer)
5 active layer 6 p-type semiconductor layer (second semiconductor layer)
7 Concave portion 8 Peripheral portion 11 N-side electrode layer (first electrode)
12 p-side electrode layer (second electrode)
13, 14 Burr 15 Anchor opening 20 Insulating film 21 N-side opening (first opening)
22 p-side opening (second opening)
31 n pad electrode (first pad electrode)
32 p pad electrode (second pad electrode)
33 Notch 40 Second insulating film 41 First through hole 42 Second through hole 43 Third through hole 44 Underlayer 45 DBR (distributed Bragg reflector)
451 Low-refractive index layer 452 High-refractive index layer 46 Metal film 47 Cap layer 51, 52 Translucent conductive film 80 Resist 81 Grow 100 Electrode material layer 110 Wafer 120 P-side electrode layer 121 Burr 130A, 130B Insulating film 131 Cavity 140 n pad electrode

Claims (9)

Preparing a wafer having a first semiconductor layer and a second semiconductor layer;
Forming a first electrode in one region on the first semiconductor layer and forming a second electrode on the second semiconductor layer provided in another region on the first semiconductor layer;
Forming an insulating film having a first opening exposing the surface of the first electrode and a second opening exposing the surface of the second electrode on the first electrode and the second electrode;
A first pad electrode that is electrically connected to the first electrode through the first opening is formed in a region on the insulating film, and is electrically connected to the second electrode through the second opening in another region on the insulating film. Forming a second pad electrode;
A step of separating the wafer into pieces,
In the step of forming the first electrode and the second electrode, at least one of the first electrode and the second electrode is formed by a lift-off method using a resist as a mask,
In the step of forming the insulating film, the insulating film is formed by forming an insulating resin on the entire surface of the first electrode and the second electrode by a spin coating method,
In the step of forming the first pad electrode and the second pad electrode, the pad electrode electrically connected to the one electrode is formed on the other electrode different from the one electrode through the insulating film. A method of forming an electrode of a semiconductor light emitting device. The one electrode has a burr formed on the peripheral edge of the upper surface by a lift-off method,
2. The electrode of a semiconductor light emitting element according to claim 1, wherein in the step of forming the insulating film, the insulating film is formed so that an upper surface of the insulating film is higher than an upper end of the burr. Forming method.   3. The insulating film is formed so that a thickness of the insulating film on the second electrode is equal to or less than a thickness of the resist in the step of forming the insulating film. The electrode formation method of the semiconductor light-emitting device of description.   4. The method for forming an electrode of a semiconductor light emitting element according to claim 1, wherein the resist has a flange portion at an end edge portion thereof. 5.   5. The electrode of a semiconductor light emitting element according to claim 1, wherein the insulating film is formed so that a thickness of the insulating film on the second electrode is 1 to 3 μm. Forming method. In the step of forming the first electrode and the second electrode, both the first electrode and the second electrode are masked with a resist having a film thickness larger than the film thickness of the first electrode and the second electrode. Formed by the lift-off method used,
In the step of forming the first pad electrode and the second pad electrode, the first pad electrode is formed on the second electrode through the insulating film, and the second pad electrode is formed on the insulating film. 6. The method of forming an electrode of a semiconductor light emitting element according to claim 1, wherein the electrode is formed on the first electrode through an electrode.   The method for forming an electrode of a semiconductor light emitting element according to claim 1, wherein the insulating resin is a photosensitive fluororesin. In the step of forming the second electrode,
A translucent conductive film is formed on the second semiconductor layer, a second insulating film having a plurality of through holes is formed on the translucent conductive film, and the second electrode is passed through the through holes. Formed on the second insulating film so as to be electrically connected to the photoconductive film;
2. In the step of forming the insulating film, the insulating film is formed on the second electrode to flatten the irregularities corresponding to the through holes on the surface of the second electrode. The electrode formation method of the semiconductor light-emitting device according to claim 1. A semiconductor structure comprising a first semiconductor layer and a second semiconductor layer provided in a region on the first semiconductor layer;
A first electrode provided in another region on the first semiconductor layer;
A semiconductor light emitting device comprising: a second electrode provided on the second semiconductor layer;
An insulating film made of a resin provided on the first electrode and the second electrode, having a first opening on the first electrode, and having a second opening on the second electrode;
A first pad electrode that is electrically connected to the first electrode through the first opening and is provided in a region on the second electrode and on the insulating film;
A second pad electrode that is electrically connected to the second electrode through the second opening and provided in another region on the first electrode and on the insulating film;
A semiconductor light emitting element, wherein the upper surface of the insulating film is provided at a position higher than an upper end of a burr formed on a peripheral edge of the upper surface of the second electrode.

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