JPS62208150A - Data access device - Google Patents

Abstract

PURPOSE:To check an error correcting means by fetching data stored in a data storing means to an arithmetic processing part through an error correcting means at the time of data access and reading/writing data by the arithmetic processing part. CONSTITUTION:In a writing route for a data register 11a and a check bit register 11b, a CPU 13 writes test data and a check bit corresponding to the test data in the registers 11a, 11b. Under said status, the functions of a syndrome generator 31, an error estimating circuit 32 and a correcting circuit 33 are made effective and correction data outputted from the circuit 33 are inputted to the CPU 13 through a data analyzer 37. The CPU 13 decides whether the test data area accurately corrected or not based on the outputted test data and the input data, and when accurate correction is decided, the nomality of an error estimating and correcting system can be recognized.

Description

[Detailed Description of the Invention] [Summary] Data storage means for temporarily storing data including predetermined check pits read from memory by access from an arithmetic processing unit; and an error correction means for estimating an error in the data and correcting the error, and when accessing the data, the data stored in the data storage means is taken into the arithmetic processing unit via the error correction means. In such a data access device, in order to easily check the cause of data errors, the data storage means is configured such that data can be read and written by an arithmetic processing section.

Field of Industrial Application] The present invention relates to a data access device having an error correction function for data read out from a memory, and more specifically, the present invention relates to a data access device having an error correction function for data read out from a memory. It has a data storage means for temporarily storing data contained in the data storage means, and an error correction means for estimating an error in the data based on the data stored in the data storage means and correcting the error, and when accessing the data, The present invention relates to a data access device in which data stored in the data storage means is taken into an arithmetic processing unit via an error correction means.

[Prior Art] Generally, in a system that performs memory access processing, predetermined check bits are added to originally required data when writing data to the memory in order to improve reliability when reading data from the memory. is added, and if an error such as bit inversion occurs when reading the data, it has a function to correct the error based on the entire read data including check pits.

Conventionally, the λ1 configuration of a data access device with an error correction function used in this type of system temporarily stores data including predetermined check pits read from memory by access from a processing unit (CPU). and an error correction circuit (ECC circuit) that estimates errors in the data based on the data held in the buffer and corrects the errors. The data held in the memory is taken into the arithmetic processing section through an error correction circuit.

[Problems to be Solved by the Invention] By the way, in the conventional data access device having the above-mentioned configuration, there is usually a limit to the function of error correction means such as an error correction circuit (ECC circuit). If an error occurs, the occurrence of the error can be recognized but cannot be corrected. In such a situation, conventional data access devices do not give any consideration to checking the cause of error occurrence (particularly related to hardware).

Therefore, when an error like the one described above occurs when reading data, the arithmetic processing unit (CPU) cannot know the cause of the error.

That is, for example, even if the arithmetic processing unit writes a test data along with predetermined check pits to the memory, and then reads out the same data and recognizes the error, it is necessary to check whether the cause of the error is on the memory side or not, and to correct the error. It is not possible to directly confirm whether it is in the means itself.

This is because the data access device cannot handle data separated from the memory and cannot check the error correction means alone.

Therefore, an object of the present invention is to make it possible to handle data separated from the memory and to check the error correction means alone.

[Means for Solving the Problems] As shown in FIG. It has a data storage means 3 for temporarily storing data, and an error correction means 4 for estimating errors in the data based on the data stored in the data storage means 3 and correcting the errors. This is based on a data access device in which the data stored in the data storage means 3 is taken into the arithmetic processing unit 1 via the error correction means 4. The technical means is to convert the data storage means 3 into an arithmetic processing unit 1.
This makes it possible to read and write data.

[Function] The arithmetic processing section 1 stores the data storage means 3 independently of the memory 2.
Write and read data to and from. Here, it becomes possible to provide the arithmetic processing unit 1 with a function related to checking the error correction means 4.

For example, the arithmetic processing section 1 writes predetermined test data together with a predetermined check bit into the data storage means 3. Then, the data written in the data storage means 3 is taken in by the arithmetic processing section 1 via the error correction means 4. Then, if the output test data (including check pins 1 to 1) match the imported data, it is determined that the error correction means 4 is normal, and if the respective data do not match, it is determined that the error correction means 4 is abnormal. The arithmetic processing unit 1 recognizes each.

[Embodiments of the invention] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a block diagram showing an example of a data access device according to the present invention.

In the figure, 11a is a data register that stores necessary data, 11b is a check bit register that stores a predetermined check bit that is paired with the data stored in the data register 11a, and 12 is an error correction circuit (hereinafter referred to as FCC). 13 is a calculation processing unit (hereinafter referred to as CP).
Basically, for data including a predetermined check bit read out by memory access by the CPU 13, the original data portion is stored in the data register 1.
1a, the check bit portion is temporarily stored in the check bit register 11b, and both stored data are paired and sent to the CPU via the FCC circuit 12.
13.

Here, the specific configuration of the FCC circuit 12 will be explained.

31 is a syndrome generator which inputs the data in the data register 11a and the check bit in the check bit register 11b as a pair and creates information regarding the error, that is, a syndrome based on the paired bit data; 32 is a syndrome generator 33 is a bit output from the error estimation circuit 32; 33 is a bit output from the error estimation circuit 32; 33 is a bit output from the error estimation circuit 32; This is a correction circuit that processes data according to a predetermined algorithm and outputs correction data for the pair of bit data as a result. Note that the syndrome generator 31, error estimation circuit 32, and correction circuit 33
The specific configuration is not particularly different from that of a general FCC circuit.

On the other hand, when data to be output from the memory is output from the CPU 13, the data aligner 34 transfers the data to the data aligner 36.
is a check bit generator that creates corresponding check bits based on the input data. Furthermore, the check bit generator 34 is further configured to receive the data stored in the data register 11a via a data aligner 36.
The configuration is such that check hits can be created based on the data.

Note that the ECC circuit 12 is a syndrome generator 3.
The syndrome created in step 1 is stored in the syndrome register 35.
It is configured to be saved and read in 1rI. In addition, the correction data from the correction circuit 33 and the syndrome [1-me] stored in the syndrome register 35 are output to the CPLJ 13 side via the data aligner 37, and the check bit in the check bit register 1ib is The data is transmitted to the CPLJ 13 only through the data aligner 37 without any special processing related to error correction within the ECC circuit 13.

Here, the CPU 13 can access the data register 11a and the check bit register 11b independently, and can also access the check bit generator 34. The data flow at the time of access is as follows.

Reading from data register 11a> Data register 11a→ ■Data aligner 36→ ■Correction circuit→ ■Data aligner 37→ ■Transceiver 3→ ■→CPU 13 At this time, the function of the correction circuit 33 is canceled and the correction is performed. It is assumed that data does not change between input and output to the circuit 33.

Writing to data register 11a> CPU 13→ ■Transceiver 4→ ■Data aligner 36→ ■Correction circuit 33→ ■Transceiver T2, Tl→ ■→Reading from check pit register 11b> Check pit register 11b→ ■Data aligner 37→ ■Transceiver 3→ ■→Write to CPU13 check pit register 11b> CPU, 13→ ■Transceiver 4→ ■Data aligner 36→ ■Correction circuit 33→ ■Transceiver T2, Tl→ ■Multiplexer 14→①→Check pit register 11b At this time, it is assumed that the function of the correction circuit 33 is canceled and the data does not change between the input and output to the correction circuit 33.

Further, the other input to the multiplexer 14 is a check bit from the memory side.

Readout of check bit generator 34> Data register 11a→ Data aligner 36→ Check pit generator 34→ ■Data aligner 37→ ■→CPL 13 or check bit generator 34→ ■Transceiver T2, Tl→ ■Multiplexer 14→ ■Check pit Register 11b→ ■Data aligner 37→ →CPU 13 In each of the above cases, the data set in the data register 11a becomes input data to the check bit generator 34.

Next, a hard check of the FCC circuit 12 will be specifically explained.

The CPU 13 writes test data and check pits corresponding to this test data to the data register 11a1 and the check bit register 11b, respectively, using the write path to the data register 118 and check pit register 11b described above regarding error estimation and correction system checking. . In this state, the functions of the syndrome generator 31, error estimation circuit 32, and correction circuit 33 are enabled, and the CPU 13 inputs correction data output from the correction circuit 33 via the data aligner 37. And CPU1
3 determines whether or not the test data has been correctly corrected based on the outputted test data and input data; for example, if it is determined that the test data has been correctly corrected,
Recognize the normality of error estimation and correction systems.

Furthermore, by comparing the output test data with the syndrome stored in the syndrome register 35, the CPU 13 can perform further individual checks.

Regarding the check of the check bit generation system, the CPU 13→Test data is written to the data register 11a using the write path described above. In this state, the function of the check bit generator 34 is enabled, and the CPU 13 reads the check pits created by the check bit generator 34 based on the test data inputted through the data aligner 36 through the above-mentioned route. Then, the CPU 13 determines whether or not the read check bit is a check bit of an expected value for the test data. For example, when determining that it is a check bit of an expected value, the CPU 13 determines whether the check pit creation system is normal or not. Recognize.

As described above, according to this embodiment, the data register 11
a and the check pit register 11b can be accessed independently by the CPU 13.
The LJ 13 can now freely supply data to the ECC circuit 12 via these registers. Therefore, F.C.
Tick can be performed by the C circuit 12 alone.

In this way, if it becomes possible to check the FCC circuit 12 alone, if an error occurs during memory access, it will be possible to determine whether there is an abnormality on the memory side or on the data access device side, especially the ECC circuit 12. It becomes possible to easily determine whether it is present or not. That is, when the error occurs, if it is determined that the ECC circuit 12 is normal by the above-described check, it is possible to determine that the error is caused by an abnormality on the memory side. If it is determined that 12 is abnormal,
It can be determined that the error is at least caused by an abnormality in the ECC circuit 12.

Incidentally, a plurality of data access devices 10 having the above configuration are provided for the memory 20, for example, as shown in FIG. Assuming a system in which access is possible, each data access device 10 connects the registers in each data access device 10 to system bus B.
It is also possible to make it accessible via .

In this way, the hardware scale for data transmission between each data access device 10 will not be increased more than necessary.

[Effects of the Invention] As explained above, according to the present invention, since the data storage means is capable of reading and writing data by the arithmetic processing unit, it becomes possible to check the error correction means alone, and data is stored from the memory. It becomes possible to easily know the cause of an error that occurs during reading.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an example of a data access device according to the present invention, and FIG. 3 is a block diagram showing an example of a system to which the data access device according to the present invention is applied. . 1... Arithmetic processing unit 2... Memory 3... Data storage means 4... Error correction circuit 10... Data access device 11a... Data register 11b... Check pit register 12... Error correction circuit (ECC circuit) 13... Arithmetic processing unit (CPU) 31... Syndrome generator 32... Error estimation circuit 33... Correction circuit 34... Check pit generator patent applicant
Fujitsu Ltd.

Claims (1)

[Claims] The memory (2) is accessed from the arithmetic processing unit (1).
a data storage means (3) for temporarily storing data including predetermined check bits read from the data storage means (3); and an error in the data is estimated based on the data stored in the data storage means (3), and the error is corrected. and an error correction means (4) for reading the data stored in the data storage means (3) into the arithmetic processing unit (1) via the error correction means (4) when the data is accessed. A data access device characterized in that the data storage means (3) is capable of reading and writing data by an arithmetic processing unit (1).