JPS62242245A - Data checking device in data transfer route - Google Patents

Abstract

PURPOSE:To detect the defective hardware of a data buffer by providing two data buffers having entirely the same function and executing a longitudinal redundancy code (LRC) process. CONSTITUTION:To data buffers 3, 4 having entirely the same function are provided. An LRC generating circuit 8 generates an LRC value B based on the output of an input register 2 and an LRC generating circuit 9 generates an LRC value C based the output of the data buffer 4. An LRC generating circuit 7 generates an LRC value A based on input data, and an LRC generating circuit 10 generates an LRC value D based on the output of an output register 6. LRC values A, C are inputted to an arithmetic circuit 11, LRC values B, D are inputted to an arithmetic circuit 12, and output A*C, B*D are inputted to a comparator 13, and judged whether A*C=B*D is satisfied or not.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data checking device in a data transfer path that detects data errors due to hardware failures on the data transfer path, and in particular, to Suitable for devices with data buffers that store
Concerning a check device.

[Conventional technology]

As a data check method in the conventional data transfer path, Longitudinal Redundancy Code (Longitudinal Redundancy Code) is used.
yCode, hereinafter abbreviated as LRC. ) is generally known. LRC is a well-known code that generates a series of data series by associating the previous and subsequent data in order from the previous data according to a certain rule. It is used to check for data errors on the data transfer path by comparing the generated LRC values.

Next, a specific example of the LRC generation circuit will be described using FIGS. 2 and 3.

Figure 2 shows LRC when one piece of data consists of one byte.
An example of a generation circuit is shown, and eight exclusive OR circuits 140 to 1 are shown.
47 and one flip-flop 150. Now, n pieces of data that are input continuously
Let us consider a case where LRC processing is performed on l to Data n. First, the flip-flop 150 receives a reset signal at its reset terminal R and is put into a reset state. Next, when data Data 1 to Data n are input continuously,
A trigger signal is input to the trigger terminal T of the flip-flop 150 each time.

As a result, the output value LRC[
3itO=LRCBit7 is as follows.

L RCBit O=Data OBit O■Dat
a I Bit O■...■Data n BitO L RCBit7 = trataOBit7■Data
I Bit 7■...■Data Bit7 In the above formula, Data OBit O means the first bit of the first data Data O, and the others have the same meaning. Also, in the above equation.

The symbol ■ means exclusive-OR logic.

FIG. 3 shows an LRC generation circuit that generates the sum of each piece of data that is continuously input.Before data transfer, the adder 16 receives a reset signal at the reset terminal R and is put into a reset state. Next, when Data O to Data n are continuously input to input terminal A.

Each time, a trigger signal is input to the trigger terminal T, and addition processing with the feedback value input to the input terminal B is performed. As a result, the LRC value output from the terminal (A+B) of the adder 16 is as follows.

LRC value = Data O+ Data 1 + −+
Next, a specific example of detecting errors in data transfer using the above-mentioned LRC will be described with reference to FIGS. 4 and 5. FIG. 4 shows data transfer in a disk device, a disk control device, and a channel device used in a computer system. In FIG. 4, in the case of write data transfer in which data is written to the disk device 19, the data is sent from the channel device 17 and transferred to the channel interface logic unit 20 in the disk controller 18 and data buffer input/output data control. Via the logic section 21 and the device interface logic section 22.

The data is sent to the disk device 19. In addition, the disk device 19
In the case of read data transfer to read data from
The data transfer path is the opposite of that for write data transfer.

FIG. 5 is a block diagram showing details of the data buffer input/output data control logic unit 21 in the disk controller 18 shown in FIG. This is an example. In FIG. 5, data is input to input register 1 and passes through data buffer input/output data control logic 21 via input register 2, data buffer 23, and output registers 5 and 6. In FIG.

Data is set in the input register 1 when there is a data acceptance request from the channel interface logic unit 20 (during write data transfer).

Or when there is a data acceptance request from the device interface logic section 22 (during read data transfer).

The conditions for writing data into the data buffer 23 are that data is prepared in the input/output register 2 and there is a free area in the data storage area of the data buffer 23.

The conditions for reading data from the data buffer 23 are that the output register 5 is empty and there is data to be read in the data buffer 23.

Note that addressing for writing and reading data to and from the monitor buffer 23 is performed using the write address pointer 28 and the read address pointer 2, respectively.
9 is selected and performed by the selector 30.

The values of these address pointers 28 and 29 are incremented by +1 by the +1 circuit 31 after accessing the data buffer 23, so that the series of input data is addressed sequentially on the data buffer 23. .

Output data from the output register 6 is taken into the channel interface logic section 20 (during read data transfer) and into the device interface logic section 22 (during write data transfer).

Furthermore, in the LRC generation circuits 7 to 10, data is taken in at the following timing.

(a) The LRC generation circuit 7 takes in the data at the timing when the data is set in the input register 1.

(b) The LRC generation circuit 8 takes in the data at the timing when the data is written into the data buffer 23.

(c) The LRC generation circuit 9 takes in the data at the timing when the data is set in the output register 5.

(d) The LRC generation circuit 10 takes in the output data of the output register 6 at the timing when the data is taken into the channel interface logic section 20 or the device interface logic section 22.

(i) When all the data written in the data buffer 23 is read out and the data transfer is completed, it is determined whether the output values of the LRC generation circuits 7 and 8 are equal or not.
It is determined by the RC determination circuit 24, and the LRC generation circuit 8,
The LRC determination circuit 25 determines whether the output values of the LRC generation circuits 9 and 10 are equal, and the LRC determination circuit 26 determines whether the output values of the LRC generation circuits 9 and 10 are equal. If any of the LRC determination circuits 24, 25, and 26 determines that they are not equal, it is assumed that there is a hardware defect on the data transfer path, and the OR circuit 27 detects this as a data error.

(it) Either only part of the data written to the data buffer 23 has been read out, or the data written to the data buffer 23 has been processed by the data buffer 23, and the processed data has been read out. .

When the data transfer is completed, the LRC generation circuit 7.8
The LRC determination circuit 24 determines whether the output values of the LRC generation circuits 9 and 10 are equal, and the LRC determination circuit 26 determines whether the output values of the LRC generation circuits 9 and 10 are equal. If either of the LRC determination circuits 24 or 26 determines that they are not equal, it is assumed that there is a hardware defect on the data transfer path, and the OR circuit 27 detects this as a data error.

The difference between (i) and (ii) above is in the case of (it).

Check whether the outputs of the LRC generation circuits 8 and 9 are equal or not.
The point is that the determination circuit 25 is not used to check. this is, (
In the case of (it), the data input to the data buffer 23 and the data output from the data buffer 23 are different, so the output values of the LRC generation circuits 8 and 9 are naturally not equal.

Incidentally, as a known example related to the above-mentioned prior art, there is an invention disclosed in Japanese Patent Application Laid-Open No. 59-202564. The gist of the invention disclosed in the above publication is as described in (ii) above.
The object of the present invention is to improve the data checking method in the case where a part of the data written in the data buffer is read out.

In other words, the data check method shown above (it) is
Since the output values of the LRC generation circuits 8 and 9 are not compared, there is a problem in that even if there is a hardware defect in the data buffer 23 and a data error occurs, it cannot be detected.

In order to eliminate this, the invention described in the above publication performs an LRC check even when only a part of the data in the data buffer is needed by reading unnecessary data, thereby improving the reliability of the device. trying to improve.

However, as a means of realizing data checking, data
All data written in the buffer is read out, including data that is unnecessary as transfer data, and each time data is read out from the data buffer using the down counter, these data are transferred to LR.
input to the C generation circuit and count/count this counter.
Go down. Then, when the counter value reaches 11011, the subsequent data is determined to be data to be transferred, and is transferred from the data buffer to the next stage register.

In this way, all of the data written in the data buffer is read, and the L
This is intended to enable data checking by generating an RC value and comparing this LRC value with the LRC value generated when writing to the data buffer, and the data check in the data transfer path of the present invention, which will be described later. It is different from the method.

[Problems to be solved by the invention] As mentioned above, in the conventional technology, when only a part of the data input to the data buffer is output, or when the data is processed in the data buffer ( In the above case (...), the data input to the data buffer and the data output from the data buffer are
L RC is not judged. Therefore, there is a problem in that even if there is a hardware defect in the data buffer, it cannot be detected.

To explain specifically using FIG. 6, in the case (if) above, the output values of the LRC generation circuits 8 and 9 are
Even if there is a hardware defect in the data buffer 23, it cannot be detected.Conversely, the LRC judgment circuits 24 and 26 are not judged by the LRC generation circuit 7.
8 and LRC generating circuits 9 and 10, it is determined that there is no data error.

The present invention has been made in view of the problems of the prior art described above, and is in the case of (it) above, that is, when input data is processed such that only a part of the data input to the data buffer is output. Even in.

It is an object of the present invention to provide a data chuck method in a data transfer path that can detect a defect in a data buffer as a data error.

[Means for solving problems]

The data checking device in the data transfer path of the present invention includes first means for temporarily holding input data, and receiving and holding data output from the first means, and processing the data as necessary. and a second means for outputting the
This is applied to a data transfer path consisting of a third means that temporarily holds data output from the first means and then outputs the data, and has the following characteristics.

That is, a first LRC generating means that generates an LRC value based on data input to the first means;
a second LRC generating means that generates an LRC value based on data output from the means; and a second LRC generating means that holds data output from the first means and processes and outputs the data as necessary. a fourth means having exactly the same function as the second means; a third LRC generating means for generating an LRC value based on the data output from the fourth means; and an output from the third means. a fourth LRC generation means for generating an LRC value based on the data to be generated; and a first LRC generation means for calculating an LRC value outputted from the first LRC generation means and an LRC value outputted from the third LRC generation means. calculation means,
a second calculation means for calculating the LRC value output from the second LRC generation means and the LRC value output from the fourth LRC generation means; and outputs of the first calculation means and the second calculation means. It is characterized in that it is configured to include a comparison means for detecting coincidence/mismatch of the data and outputting a data error signal in case of mismatch.

[For production]

In the data checking device in the data transfer route of the present invention described above, the second means and the fourth means have exactly the same functions and execute data holding, processing, etc. in exactly the same way. As a result, if a hardware failure occurs in the second means, the second means and the fourth means output mutually different data. Therefore, based on the data output from the fourth means, the LRC value generated by the third LRC generation circuit and the data output from the second means (via the third means) Based on this, the LRC value is different from the LRC value generated by the fourth LRC generation means. As a result, the first LR
The LRC value generated by the C generation means and the second LR
Even if the LRC values generated by the C generation means are equal, the output of the first calculation means and the output of the second calculation means are different values, and an error detection signal is output from the comparison means.

Therefore, according to the present invention, since the fourth means having exactly the same function as the second means is provided to perform LRC processing, the hardware of the second means, which could not be detected with the conventional technology, It becomes possible to detect defects.

[Examples] Hereinafter, the present invention will be described in more detail with reference to Examples shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a data buffer input/output data control logic section of a magnetic disk control device, and the same parts as in the conventional example shown in FIG. 5 are given the same reference numerals. Therefore, the explanation thereof will be omitted.

As shown in FIG. 1, in this embodiment, two data buffers 3 and 4 ' is entered. Then, the LRC generation circuit 8 generates the LRC value B based on the output of the input register 2. Further, the output of the data buffer 4 is input to the LRC generation circuit 9, and the LRC generation circuit 9 generates the LRC value C based on the output of the data buffer 4. And L
The RC generation circuit 7 generates an LRC value A based on input data, similar to the conventional example shown in FIG. The LRC generation circuit 10 also generates an LRC value based on the output of the output register 6, similar to the conventional example shown in FIG.

LRC values A and C output from L and RC generation circuits 7 and 9
are both input to the arithmetic circuit 11. Also, LRC (i!B) output from the LRC generation circuits 8 and 10.

C are both input to the arithmetic circuit 12. Here, the arithmetic circuits 11 and 12 both perform operations with the same content, such as an exclusive OR operation, a simple OR operation, and a simple addition. Output Arc of arithmetic circuits 11 and 12,
Both BAD and BAD are input to the comparison circuit 13, and it is determined whether or not A*C=BskewD (1) holds true. Here, the symbol 1 means an operator, such as exclusive OR operation, simple OR operation, addition, etc. as described above. If formula (1) holds true, no data error signal is output and the input register 1
, 2 and data buffers 3, 4 and output register 5,
6, it is determined that there is no hardware defect. In addition, if equation (1) does not hold, input register 1,
2. It is determined that there is a hardware defect in either data buffers 3, 4 or output registers 5, 6, and the data
An error signal is output.

Next, the operation of the above embodiment will be explained.

As mentioned above, data buffers 3 and 4 are both addressed via selector 30 and have exactly the same configuration and, as a result, have exactly the same function. Therefore, unless there is a hardware failure, the data buffers 3 and 4 output the same content data.

(a) Input registers 1 and 2 and data buffers 3 and 4
And when there is no hardware defect in the output registers 5 and 6, the operation is as in the first order.

In case (i) above (when data buffers 3 and 4 output the data as is without processing it), A=
B=C=D, and the above equation (1) is established. In addition, in the case (it) above (when the data buffer 3.4 outputs processed data such as outputting a part of the input data), A=B≠C=D, and the above (1 ) holds true. Therefore, in this case, the comparison circuit 13 detects a match and the data error signal - is not output.

(b) If there is a hardware defect in either data buffer 3 or 4 and input registers 1 or 2 and output registers 5 or 6 are normal, the following operation will occur. Said (i
) (when data buffer 3゜4 outputs the data as it is without processing it), A=B#Cf
-D. Furthermore, in the case (road) above (when the data buffers 3 and 4 output processed data such as outputting a part of the input data), similarly A=B≠C−I−
It becomes D.

Therefore, in this case, the above-mentioned equation (1) does not hold true in both cases (i) and (ii), and the comparator circuit 13 outputs a data error signal.

Therefore, it is possible to detect a hardware defect in the data buffer 3 in the case (ji), which could not be detected using the prior art.

(c) If either input buffer 1 or 2 has a hardware defect and data buffers 3 and 4 and output registers 5 and 6 are normal, the following operation is performed. Said (i
) (when data buffer 3゜4 outputs the data as is without processing it), Af-B=C
=D. Furthermore, in the case of (1i) above (when the data buffers 3 and 4 output processed data such as outputting a part of input data), A#B≠C=D. Therefore, in this case, the above-mentioned equation (1) does not hold true in both cases (i) and (n), and the comparator circuit 13 outputs a data error signal.

(d) If there is a hardware failure in either output buffer 5 or 6 and input buffers 1 and 2 and data buffers 3 and 4 are normal, the following operation occurs. Said (i
) (when data buffer 3゜4 outputs the data as is without processing it), A=B=C≠
It becomes D. In the case of (■) above (data buffers 3 and 4
(when outputting processed data such as outputting a part of input data), A=B≠0f−D. Therefore, in this case, in both cases (i) and (H, the above (1)
The equation does not hold, and the comparison circuit 13 outputs a data error signal.

In the above embodiment, the data buffer input/output data control logic unit of a magnetic disk control device was explained as an example, but the present invention is not limited to this.
It can also be applied to other data transfer routes.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to detect a hardware failure in the data buffer even when the data buffer outputs processed data such as outputting only a part of the input data. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are block diagrams showing a specific example of an LRC generation circuit,
FIG. 4 is a block diagram showing data transfer between a channel device, a disk control device, and a disk device, and FIG. 5 is a block diagram showing a specific example of a data buffer input/output data control logic unit in a conventional disk control device. . 1.2...Input register, 3,4.23...Data buffer, 5,6...Output register, 7,8,9°10...LRC generation circuit, 11.12... Arithmetic circuit, 13... Comparison circuit, 16... Adder, 17...
Channel device, 18... Disk control device, 19.
. . . Disk device, 21 . . . Data buffer input/output data control logic unit, 24, 25. 26 . . LRC judgment circuit, 28 . . . Write address pointer, 29.
...Address pointer for readout, 3o...Selector, 140-147...Exclusive OR circuit, 150...Flip-flop agent Patent attorney Tadashi Akimoto Actual Figure 2 I47

Claims (1)

[Claims] 1. A first means for temporarily holding input data; a second means for receiving and holding data output from the first means; and processing and outputting the data as necessary; 2
and a third means that temporarily holds and then outputs the data output from the means, a first L that generates an LRC value based on the input data.
RC generation means; second LRC generation means for generating an LRC value based on data output from the first means; a fourth means having exactly the same function as the second means for processing and outputting data; and a third LRC generating means for generating an LRC value based on the data output from the fourth means. , a fourth LRC generation means that generates an LRC value based on the data output from the third means, and an LRC value output from the first LRC generation means and an LRC value output from the third LRC generation means. a first calculation means for calculating the LRC value; a second calculation means for calculating the LRC value output from the second LRC generation means and the LRC value output from the fourth LRC generation means; Data in a data transfer path characterized by comprising a comparison means for detecting coincidence or mismatch between the outputs of the first calculation means and the second calculation means and outputting a data error signal in the case of a mismatch.・Check device.