JPS62207978A - Self-diagnosing device for test system - Google Patents

Abstract

PURPOSE:To obtain a self-diagnosing device which can store data in the state of matching phases by successively storing the diagnosis data of the respective parts to be diagnosed of a test system according to the clocks corrected in timing according to the respective parts to be diagnosed. CONSTITUTION:The self-diagnosis device (SD)10 having the functions to make the self-diagnosis of the respective parts constituting the test system is connected to a control device (CTL)9. A rate signal RATE is applied to the SD10 from a timing generator (TG)3 and a test pattern PAT is applied thereto from an output terminal (a) of the pattern generator (PG)1. An output signal from an output terminal of a formatter (FMT)2 is applied thereto and a response pattern D-OUT of an object to be tested (DUT)5 is applied thereto via a comparator 6. The diagnosis data of the respective parts to be diagnosed are shifted in phase relative to the clocks and therefore, the phase shifts are corrected by controlling the delay time according to a selection signal. The accuracy of fault discrimination is thus improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for performing self-diagnosis of a test system.

[Prior Art] FIG. 4 is a block diagram showing an example of a main part of a conventional LSI test device. In FIG. 4, 1 is a pattern generator (hereinafter referred to as PG), and a test pattern PAT is output from an output terminal a, and a formatter (hereinafter referred to as FMT) is output from an output terminal a.
) has been added to 2. This test pattern FA
T is modulated by a format clock F-CLK applied from a timing generator (hereinafter referred to as TG) 3, and then outputted to the test object (hereinafter referred to as 1) U via a driver 4.
(referred to as T) is added to 5. In addition, TG3 is PG
A rate signal RATE with a predetermined period is output to I and fail analyzer et (hereinafter referred to as FA) 8, and a format clock F- synchronized with the rate signal RATE is output to FMT2.
CLK and a strobe 5TRB to a digital comparator (hereinafter referred to as CMP) 7. DUT
5, when the test pattern FAT is added, D U T
5 Response pattern D-O after internal delay elapses
Output 4JT. The response pattern D-OUT is applied to one input terminal a of the CMP 7 via the level comparator 6. The other input terminal of CMP7 is PG.
The expected pattern EXP T corresponding to the test pattern FAT is added to the output terminal of I. and,
CMP7 is the expected pattern EXPT added from PGI.
and a digital signal corresponding to the response pattern D-OUT, and the comparison data C-0UT is added to FA8.

, 9 is a control device (hereinafter referred to as CT) for controlling the operation of each part.
It is connected to each part via a path.

By the way, in such a test system, if the circuit constituting the test system itself breaks down, normal test operation will not be performed.

[Problems to be solved by the invention] However, in the conventional test system, there are
The problem was that it required a considerable amount of man-hours for fault diagnosis.

The present invention has been made with attention to these points, and its purpose is to provide a test system self-diagnosis device that is capable of diagnosing a faulty circuit in the test system itself with a relatively simple configuration. be.

[Means for Solving the Problems] The present invention achieves these objects by using a format that modulates a test pattern applied from a pattern generator by a format clocker applied from a timing generator and applies it to a test object. , the test system J5 includes a comparator that compares the response pattern obtained from the test object with the expected pattern output from the pattern generator corresponding to the test pattern and outputs comparison data to the pattern generator. Means for sequentially storing diagnostic data of each part of the system to be diagnosed according to a clock whose timing is corrected according to the diagnostic target, and estimating a faulty part by comparing the stored diagnostic data with pre-stored non-defective data. The invention is characterized in that it is provided with a means to do so.

[Example J Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing essential parts of an embodiment of the present invention, and the same parts as in FIG. 4 are designated by the same reference numerals. In FIG. 1, 10 is a self-diagnosis device (hereinafter referred to as SD) that has a self-diagnosis function for each part constituting the test system.
). 5D10 via bus B
It is connected to the.

Then, in this 5t)10, the rate signal R from TG3 is
ATE is applied, a test pattern P A 1- is applied from the output terminal a of PGl, an output signal is applied from the output terminal of FMT2, and a response pattern D-OUT of DLIT5 is applied via the level comparator 6. .

FIG. 2 is a block diagram showing a specific example of the 5D10.

In FIG. 2, reference numeral 11 indicates a memory (hereinafter referred to as MR) in which the data applied from each part of the test system (on the Kinotsu side, PQl, FMT2, level comparator 6) is selected according to a selection signal SEL applied from CT19. )
Multi-break IJ- (hereinafter referred to as MPX) added to 12
It is. 13 is the address signal @A to be added to MR12
This is a counter (hereinafter referred to as CTR) that generates D. C
A clock CLA is applied to TR13 via a variable delay circuit (hereinafter referred to as DLA) 14 whose delay time limit is set according to a selection signal SEL, and 0LA1 is applied to MR12.
A clock CLB to which a predetermined delay time DTB is given by a fixed delay circuit (hereinafter referred to as DLB) 15 is added to the clock CLA outputted from the clock CLA.

The diagnostic operation of the apparatus configured as described above will be explained using the timing chart of FIG. 3.

In FIG. 3, (a) is D1. , A shows the clock CL K applied to 14, (b) shows the clock CLA applied to CTR 13 via OLΔ14,
(C) shows the dead pattern PΔT output from FMT 2, (d) shows the address signal AD applied from CTR 13 to MR 12, and (e) shows the clock signal AD applied to MR 12 via DLB 15. CL B is shown.

5D10 is controlled by the selection signal SEL during the test of CUT5 or in the diagnostic ah operation mode.
The data of each part is sent to MR1 as diagnostic data via Xil.
Store in 2. Here, the diagnostic data of each part to be diagnosed will be out of phase with respect to the clock CLK. Therefore, in this embodiment, the delay time DTA of the DLA 14 is controlled according to the selection signal SEL to give the clock CLK a predetermined delay time depending on each part to be diagnosed, thereby correcting the phase shift. In addition, the MR 12 has a clock Cl-8 to which a delay time DTB due to the L B 15 is applied to the clock CLA output from the D LA 14.
is added as a read clock.

As a result, clock CLB becomes address signals AD and M
The phase will be synchronized with the data applied via PXll, and the diagnostic data will be stored in the MR 12 in phase with the various data input to the FA8.

On the other hand, good product data for each part corresponding to each pattern address is stored in advance in CTL9 and stored in J5. and,
The diagnostic data stored in the MR 12 is compared for each pattern address to estimate the faulty part.

With this configuration, it is possible to estimate the faulty portion of the test system to a fairly narrow IT portion using the test system itself without using a measuring instrument such as an oscilloscope.

Note that the 5D10 used in the present invention can be configured almost in the same way as the 1:80, and since many hardware and software can be shared, it can be configured relatively inexpensively.

Further, the clock CLK may be an internal clock or an external clock. When an external clock is used, the accuracy of estimating the faulty part can be further improved by taking in the data of each part that is progressing simultaneously with the test of the CUT 5.

In the above embodiment, an example of an LSI test device has been described, but the present invention can also be applied to test devices using other interpolation patterns.

[Effects of the Invention] As explained above, according to the present invention, a test system self-diagnosis device capable of diagnosing a faulty circuit in the test system itself can be realized with a relatively simple configuration, and the practical effects are great. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing essential parts of an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of the SD used in FIG. 1,
Figure 3 is Taiminoguchi 1 to explain the operation of Figure 1.
! FIG. 4 is a block diagram showing an example of a main part of a conventional circuit. 1... Pattern generator (PG), 2... Format (FM), 3... Timing generator PJ (TO),
4...Driver, 5...Test object (CUT)
, 6...Level comparator, 7...Digital comparator (CMI)), 8...Fail analysis device (F
A), 9... system ti15A purchase (CTI-), 10...
・Self-diagnosis device (SD), 11...Multiplexer (
12...Memory (MR), 13...Counter (CTR), 14...Variable delay circuit (DLA)
), 15...Fixed storage circuit (DLB).

Claims (1)

[Claims] A formatter modulates the test pattern applied from the pattern generator using a format clock applied from the timing generator and applies it to the test object, and a formatter that modulates the test pattern applied from the pattern generator using a format clock applied from the timing generator and applies it to the test object, and a formatter that modulates the test pattern applied from the pattern generator and applies it to the test object. In a test system that includes a comparator that compares the expected pattern with an expected pattern and outputs comparison data to a pattern generator, diagnostic data of each part of the test system to be diagnosed is sequentially stored according to a clock whose timing is corrected according to the target to be diagnosed. What is claimed is: 1. A test system self-diagnosis device comprising: means for estimating a faulty part by comparing the stored diagnostic data with pre-stored non-defective data.