JPS636473A - Self-diagnosing device for test system - Google Patents

Abstract

PURPOSE:To judge a faulty part by generating a diagnostic clock synchronizing with the operation clock of a test system which compares an output pattern with an expected pattern and latching and comparing data on respective parts to be diagnosed with conforming article data. CONSTITUTION:A diagnostic clock generator (DCG) 10 generates the diagnostic clock D-CLK synchronizing with the operation clock of the test system according to a pattern address from a pattern generator 1. Latch circuits (LTH) 11-15 are arranged at respective parts to be diagnosed and latch diagnostic data on the respective parts according to the diagnostic clock D-CLK. The diagnostic clock D-CLK applied to the respective LTHs 11-15 has its system delay time corrected according to the position relation of a circuit to be diagnosed. The latched data is inputted to a controller CTL 9 through a bus DB and collated with previously stored conforming article data to judge whether or not there is a fault.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for performing self-diagnosis of a test system.

[Prior Art] FIG. 3 is a block diagram showing an example of a main part of a conventional LSI test device. In FIG. 3, 1 is a pattern generator (hereinafter referred to as PG), and a test pattern PAT is output from an output terminal a, and a formatter (hereinafter referred to as FMT) is output from an output terminal a.
) is added to 2. This test pattern PA
T is modulated by a format clock F-CLK applied from a timing generator (hereinafter referred to as TG) 3, and then applied to a test object (hereinafter referred to as DUT) 5 via a driver 4. Note that TG3 is PG1#
A rate signal RATE with a predetermined period is output to the fail analysis device (hereinafter referred to as FA) 8, and a format clock F-CLK synchronized with the rate signal RATE is output to the FMT2.
Outputs the digital comparator (hereinafter referred to as CMP)
7 is outputting 18 straws RB. DUT5 is
When the test pattern FAT is applied, a response pattern D-OUT is output after a delay inside the DUT 5 has elapsed. The response pattern D-OUT is the level comparator 6.
The signal is applied to one input terminal a of the CMP 7 via the input terminal a. From the other input terminal of CMP7 to the output terminal of PGI, the expected pattern EX corresponding to the test pattern FAT is inserted.
PT has been added. Then, CMP7 is the expected pattern EXPT added from PGI and the response pattern D-O.
Compare the digital signal compatible with UT and obtain comparison data C.
-〇IJT has been added to FA8. Reference numeral 9 denotes a control device M (hereinafter referred to as CTL) for controlling the operation of each section, and is connected to each section via a bus B.

By the way, in such a test system, if the circuit constituting the test system itself breaks down, normal test operation will not be performed.

Therefore, as a method for diagnosing such circuit failures,
For example, from the analysis results of FA8 when the output of FMT2 is applied directly to CMP7, and the analysis result of FA8 when the output of FMT2 is applied to CMP7 via driver 4 and level comparator 6 with DUT 5 removed, it is possible to determine whether a failure occurs. Estimation of the circuit is being carried out.

Problems to be Solved by Invention C] However, according to such a method, a faulty circuit cannot be accurately identified.

In addition, since the diagnosis is performed with DUT5 removed,
Diagnosis cannot be performed in real time.

Furthermore, since the estimation is based on the analysis results of FA8 used in the test of DUT5, the diagnostic results lack objectivity.

The present invention has been made with attention to these points, and its purpose is to provide a test system self-diagnosis device that can diagnose faulty circuits in a test system in real time and with high accuracy with a relatively simple configuration. It is in.

[Means for Solving the Problems] The present invention achieves the above object, and includes a formatter that modulates a test pattern applied from a pattern generator using a format clock applied from a timing generator, and applies the modulated test pattern to a test object; In a test system that includes a comparator that compares a response pattern (q) from a test object with an expected pattern output from a pattern generator corresponding to the test pattern and outputs comparison data to the pattern generator, a diagnostic clock generator that generates a diagnostic clock synchronized with the clock;
A latch circuit is placed in each part of the test system to be diagnosed and successively latches the diagnostic data of each part according to the diagnostic clock, and the diagnostic data latched in these latch circuits is fetched and compared with pre-stored non-defective data to find the faulty part. The invention is characterized by providing a means for determining.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, and the same parts as in FIG. 3 are given the same reference numerals. 1st
In the figure, 10 is a diagnostic clock generator (hereinafter referred to as DCG) which generates a diagnostic clock D-CLK synchronized with the operating clock of the test system according to a pattern address applied from the PGI. Reference numerals 11 to 15 are latch circuits (hereinafter referred to as LT
). That is, LTI-111 is
Diagnostic test applied via H15 clock terminal
-CLK is latched in accordance with a clock applied via a delay circuit 16 that provides a predetermined delay time corresponding to the delay time of this diagnostic clock D-CLK. LTH12 is
The output data of FMT2 is latched according to the diagnostic clock D-CLK output from DCGlo. LTH13 latches the output data of driver 4 according to the diagnostic output clock D-CLK applied via the clock terminal of LTH12. The LTH14 latches the output data of the level comparator 6 according to the diagnostic clock D-CLK applied via the clock terminal of the LTH13. LTH1
5 is the data applied to input terminal a of CMP7.
It is latched according to the diagnostic clock D-CLK applied via the clock terminal of H14. Here, each LTI-1
Since the diagnostic clocks D-CLK added to signals 11 to 15 are transmitted via signal lines that are wired sequentially according to the positional relationship of the circuits to be diagnosed, the system delay time has been corrected. And each of these LTH11~
The data latched in L block H15 is transferred to C via bus DB.
The data is taken into the TL9 and compared with pre-stored non-defective product data to determine whether or not there is a failure in the corresponding circuit.

The diagnostic operation of the apparatus configured in this way will be explained.

FIG. 2 is a timing chart for explaining the operation of the LTH 13. In FIG. 2, (a) shows the state of data 0-IN applied from the driver 14 to the DUT 5, and (t)) shows the state of the data 0-IN applied to the DUT 5 from the driver 14, and (t)) shows the state of the data 0-IN applied to the DUT 5 from the driver 14, and
Indicates the diagnostic clock D-CLK applied to TH13,
(C) shows data D13 latched in LTH13 according to diagnostic clock D-CLK. The data D13 latched in the LTH 13 in this way is taken into the CTL 9 via the bus DB as described above, and is compared with pre-stored non-defective data to determine whether there is a failure up to the output terminal of the driver 14. be done.

For example, assume that the test results of a plurality of DUTs 5 are determined to be failed by the FA8. In this case, it is necessary to check whether 00T5 is really defective or whether the test system is malfunctioning and DIJT5 is determined to be defective. Such a check can be performed by comparing the data latched in each LTH 11 to 15 with the non-defective data in the CTL 9 according to the diagnostic clock 1)-CLK as described above. That is, for example, if the data of the LTH 12 is determined to be a failure on the bus, and the data of the LTH 13 is determined to fail, it can be determined that the driver 4 is out of order. Such failure parts can be identified in detail by adding latch circuits to each part.

With this configuration, the presence or absence of a failure in the test system and the failure part can be diagnosed in real time at a high speed synchronized with the test cycle of D tJ T 5. In addition, when diagnosing the test system, DIJT
Since the FA8 used in the test No. 5 is not used, a high degree of objectivity can be obtained for the diagnostic results.

In addition, in the above embodiment, an example of LSI test@equipment was explained, but other test V using the same type of pattern is also possible.
, , m can also be applied.

[Effects of the Invention 1] As explained above, according to the present invention, a test system self-diagnosis device that can diagnose faulty circuits in a test system in real time and with high precision can be realized with a relatively simple configuration, and has practical effects. is big.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a block diagram showing an example of the main parts of a conventional circuit. It is a diagram. 1...Pattern generator (PG), 2...Formatsuta (FMT), 3...Timing generator (TG), 4
...Driver, 5...Test object <DUT), 6
... Level comparator, 7... Digital comparator (CMP), 8... Fail analysis device (FA),
9... Control device (CTL), 11-15... Latch circuit (LTH), 16... Delay circuit.

Claims (1)

[Claims] The test pattern applied from the pattern generator is modulated by the format clock applied from the timing generator, and the formatter is applied to the test object, and the response pattern obtained from the test object and the output from the pattern generator corresponding to the test pattern. In a test system that includes a comparator that compares the expected pattern with an expected pattern and outputs comparison data to a pattern generator, a diagnostic clock generator that generates a diagnostic clock synchronized with the system operating clock and a diagnostic clock generator that generates a diagnostic clock that is synchronized with the system operating clock and Latch circuits arranged to sequentially latch the diagnostic data of each part according to the diagnostic clock, and a means for fetching the diagnostic data latched by these latch circuits and comparing them with pre-stored non-defective data to determine a faulty part. A test system self-diagnosis device characterized by being provided with.