JPH0756505B2 - Test system self-diagnostic device - Google Patents

Description

Description: [Industrial field of use] The present invention relates to an apparatus for self-diagnosis of a test system.

[Prior Art] FIG. 3 is a block diagram showing an example of a main part of a conventional LSI test apparatus. In FIG. 3, reference numeral 11 is a pattern generator (hereinafter referred to as PG), and a test pattern PAT is output from the output terminal a and a formatter (hereinafter referred to as FMT) 12
Is added to the input terminal b of. This test pattern PA
The T is modulated by a format clock F-CLK applied from a timing generator (hereinafter referred to as TG) 13 and then added to a pin d of a test object (hereinafter referred to as DUT) 15 via a driver 14. TG13 is PG11
The rate signal RATE having a predetermined cycle is output to the FMT12, the format clock F-CLK synchronized with the rate signal RATE is output to the FMT12, and the strobe STRB is output to the CMP17. DUT15
Outputs the response pattern D-OUT from the pin e after the delay inside the DUT 154 has elapsed when the test pattern PAT is applied. The response pattern D-OUT is applied to the input terminal f of the digital comparator (hereinafter referred to as CMP) 17 via the level comparator 16. Reference numeral 18 is a delay line (hereinafter referred to as DL) that gives a predetermined delay for correcting the system delay to the expected pattern EXPT output from the output terminal g of PG11 at the same time as the test pattern PAT, and its output terminal is CMP17. It is connected to the input terminal h.

As a result, CMP17 is expected pattern E added from PG11.
XPT and the digital signal corresponding to the response pattern D-OUT are compared, and the comparison data C-OUT is added to the input terminal i of PG11. The system delay means the phase difference between the test pattern PAT applied to one input terminal f of the CMP 17 and the expected pattern EXPT applied to the other input terminal h with the terminals d and e of the DUT 15 short-circuited. , DL18 is these CMP16
It is used to match the timing of the test pattern PAT applied to one input terminal f and the expected pattern EXPT applied to the other input terminal h.

By the way, in such a test system, FMT12
If the CMP16 or CMP16 itself fails, normal test operations will not be performed.

[Problems to be solved by the invention] However, in the conventional test system, these FMT12 and CMP are used.
There is no device for efficiently and quickly diagnosing the failure of the 17 itself, and there is a drawback in that man-hours equivalent to the failure diagnosis are required.

The present invention has been made in view of such a point, and an object thereof is to provide a test system self-diagnosis apparatus capable of quickly performing failure diagnosis with a relatively simple configuration.

[Means for Solving the Problems] The present invention that achieves the above object includes a formatter that modulates a test pattern applied from a pattern generator with a format clock applied from a timing generator, and adds the formatter to a test object. In a test system including a response pattern obtained from the test object and an expected pattern output from the pattern generator corresponding to the test pattern and outputting a comparison data to the pattern generator, A first OR gate for inputting to the formatter a test pattern for testing the test object to be added and a test pattern for diagnosis applied from the test pattern generating means for diagnosis, and a test object added from the timing generator. Format clock and diagnostics for testing Second OR gate for inputting to the formatter the format clock for diagnosis added from the format clock generating means for use in the test, and an expected pattern for testing the test object and an expected pattern for diagnostic use added from the pattern generator. The third OR gate for inputting the expected pattern for diagnosis added from the above into the comparator, and the test pattern for testing output from the formatter at the time of testing the test object are output from the test object in addition to the test object. Data selecting means for adding a response pattern to the comparator, and a diagnostic test pattern output from the formatter in the diagnostic mode to the comparator, and a test pattern output from the formatter in the diagnostic mode and the comparator output ratio And diagnostic means for taking in comparison data and diagnosing the operation of these formatters and comparators.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention, and the same parts as those in FIG. 3 are designated by the same reference numerals. First
In the figure, reference numeral 18 denotes an arithmetic and control unit (hereinafter referred to as a CPU) having a function of controlling the operation of each part and a self-diagnosis operation of the test system according to the present invention, including data lines D0 to D2 and write / read signal lines. It is connected to the register 19 via W / and to the gate 20 via the data lines D0 to D4 and the write / read signal line W /. Register 19 has data lines D0 to D2 from CPU 18.
The data of the expected pattern EXPT for diagnosis, the format clock F-CLK, and the test pattern PAT sent via the write / read signal line W / are stored in accordance with the write signal W applied from the CPU 18. Register 19
The data of the expected pattern EXPT for diagnosis, the data format clock F-CLK, and the test pattern PAT stored in (1) are respectively applied to one input terminals of the OR gates OG0 to OG2. The expected pattern EXPT is applied from the output terminal g of PG11 to the other input terminal of the OR gate OG0, the format clock F-CLK is applied from TG13 to the other input terminal of the OR gate OG1, and the other input of the OR gate OG2 is applied. The test pattern PAT from the output terminal a of PG11 is added to the terminal. The output terminal of the OR gate OG0 is CM
It is connected to one input terminal of P17 and to the data line D0 via the gate 20, and the output terminals of the OR gates OG1 and OG2 are connected to the input terminal of the FMT12 and also to the gate 2
It is connected to the data lines D1 and D2 via 0. The output data of the FMT12 is, for example, a control signal SEL− added from the CPU 18.
It is applied to the driver 14 via a multiplexer (hereinafter referred to as MUX) 21 driven according to A, and is also applied to one input terminal of a MUX 22 driven according to a control signal SEL-B applied from the CPU 18, for example. The output data of the level comparator 16 is added to the other input terminal of the MUX 22. The output data of the MUX 22 is applied to the other input terminal of the CMP 17 and is also applied to the data line D3 via the gate 20. Output data of CMP17 C-OUT
Is applied to the input terminal i of PG11 and is also applied to the data line D4 via the gate 20. The gate 20 is CP
The enable state is set according to the read signal applied from U18 via the write / read signal line W /, and the register
It will operate complementarily to 19.

The diagnostic operation of the FMT 12 and the CMP 17 in the device thus configured will be described with reference to the timing chart of FIG.

In FIG. 2, (a) shows a test pattern PAT applied from the CPU 18 to the FMT 12, and (b) shows a format clock F-CLK applied from the CPU 18 to the FMT 12.
(C) shows a test pattern of return zero (hereinafter referred to as RZ) output from FMT12, (d) shows a non-return zero (hereinafter referred to as NRZ) and test pattern output from FMT12, and (e) shows RZ. Corresponding to the test pattern
Expected pattern EXPT1 added from CPU18 to CMP17 is shown, and (f) shows expected pattern EXPT2 added to CMP17 corresponding to the NRZ test pattern.

By setting the diagnostic mode, the transmission of each pattern for executing the test of the DUT 15 from the PG11 and TG13 is prohibited, and each diagnostic pattern is output from the CPU 18.

First, the CMP 17 is basically configured as a logic circuit that outputs an exclusive OR of the output data of the OR gate OG0 and the output data of the MUX 22. Therefore, it is possible to diagnose whether the operation of the CMP 17 is good or bad based on the correspondence between the expected pattern EXPT applied from the CPU 18 to the CMP 17 and the output data of the MUX 22 read by the CPU 18.

Next, the diagnosis of the operation of the FMT 12 will be described. In this case, the MUX22 is set to selectively output the output data of the MUX21. Then, for example, if the MUX 21 is set to output the RZ pattern, EXPT1 is added as the expected pattern. This will ensure correct RZ on FMT12.
If a pattern is generated, CMP1 in each section T1 to Tn
The output data C-OUT of 7 becomes "L" level. Therefore, the output data C- of the CMP 17 read by the CPU 18 in each section
Whether the operation of the FMT12 is good or bad can be diagnosed depending on whether OUT is at the “L” level or not. Also, from MUX21 to NRZ
If the pattern is set to be output, add EXPT2 as the expected pattern. As a result, if the FMT 12 correctly generates the NRZ pattern, the output data C-OUT of the CMP 17 in each section T1 to Tn becomes the "L" level as in the RZ pattern. Therefore, it is possible to diagnose whether the operation of the FMT 12 is good or not depending on whether the output data C-OUT of the CMP 17 read by the CPU 18 in each section is at "L" level.

In the above embodiment, various diagnostic patterns are directly output from the CPU 18 and the output data of each unit is captured to perform the diagnosis, but these functions are distributed to a plurality of circuits so that each circuit is a CPU. You may make it control over the control.

In addition, although the example of the LSI test apparatus has been described in the above-described embodiments, the present invention can be applied to a test apparatus using other patterns of the same kind.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a test system self-diagnosis device that can perform fault diagnosis quickly with a relatively simple configuration, and is highly effective in practice.

[Brief description of drawings]

FIG. 1 is a block diagram showing an essential part of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a block showing an example of an essential part of a conventional circuit. It is a figure. 12 …… Formatter (FMT), 16 …… Comparator (CM
P), 18 ... arithmetic control unit (CPU), 19 ... register, 20 ... gate, 21, 22 ... multiplexer.

Claims (1)

[Claims] 1. A formatter which modulates a test pattern applied from a pattern generator with a format clock applied from a timing generator to add to a test object, and a pattern corresponding to a response pattern and a test pattern obtained from the test object. In a test system including a comparator that compares the expected pattern output from the generator and outputs comparison data to the pattern generator, a test pattern for testing the test target and a test for diagnostics applied from the pattern generator. A first OR gate for inputting a diagnostic test pattern added from a pattern generating means to the formatter, a format clock for testing a test object added from a timing generator, and a format clock for diagnostics Diagnostic A second OR gate for inputting the format clock to a formatter, an expected pattern for testing a test object added from a pattern generator, and an expected pattern for diagnosis added by expected pattern generation means for diagnosis. In addition to the third OR gate to be input to the test object, the test pattern output from the formatter when testing the test object is added to the test object, and the response pattern output from the test object is added to the comparator. A data selecting means for adding a diagnostic test pattern output from the formatter to the comparator; and a test pattern output from the formatter and a comparison data output from the comparator in the diagnostic mode. A test system self-diagnosis device comprising: diagnostic means for diagnosing the operation of the test system.