JP3066072U - Semiconductor test equipment - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A semiconductor test apparatus having an analog measurement unit,
Using an external measuring instrument, the debugging efficiency of the analog measurement test program is increased, and the diagnosis of the device is facilitated. A semiconductor test apparatus having an analog measuring unit, in which a test processor controls the entire apparatus, wherein a predetermined clock is generated from a burst wave of a clock signal generated by an event master of the analog measuring unit and supplied to an analog module. The semiconductor test apparatus includes an event trigger terminal that selects a signal as an event trigger, transmits the event trigger to the test head, and supplies the test head to an external measuring instrument.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 This invention relates to a semiconductor test apparatus having an analog measurement unit for testing an analog LSI (large-scale integrated circuit) or a mixed LSI, and is used for debugging a test program related to analog measurement and diagnosing the semiconductor test apparatus. Also, the present invention relates to a semiconductor test apparatus that supplies a necessary trigger signal to an external measuring instrument to drive the external measuring instrument, and performs debugging and checking using the external measuring instrument.

[0002]

[Prior art]

 The development of semiconductor LSI has been remarkable, and it was previously classified into logic LSI, memory LSI, analog LSI, etc. according to the function of the LSI. Some LSIs have been integrated. For example, a one-chip television LSI, audio LSI, communication LSI MODEM, CODEC, etc. can be said to be typical "mixed LSI" devices. In other words, a mixed LSI is an LSI in which an analog section such as an A / D converter and a D / A converter and a memory section are mixed in addition to a logic section.

There is a mixed semiconductor test apparatus for testing the above-mentioned mixed LSI. There is also an analog semiconductor test apparatus for testing only an analog LSI. Furthermore, recently, a comprehensive semiconductor test device equipped with a section for testing analog circuits has also been developed for digital semiconductor test devices. In this specification, these are collectively referred to as “semiconductor test equipment”. First, a conventional so-called mixed semiconductor test apparatus will be described.

FIG. 4 is a schematic block diagram of a conventional semiconductor test apparatus, FIG. 3 is a schematic external view, and FIG. 5 is a conceptual diagram for measuring a DUT 22 which is a mixed LSI. This will be described mainly with reference to FIG. The semiconductor test apparatus is roughly classified into a work station (EWS) 50, a main frame (MF) 30, and a test head (TH) 20. The work station 50 is operated by an operator and includes a test processor 51, a display unit 52, and input / output means such as a keyboard (not shown).

[0005] The test processor 51 controls the entire apparatus, and supplies a control signal to each unit via a tester bus 53 and a VXI bus 54. The VXI bus 54 is a system bus for modular measuring instruments, which is being standardized in the United States. The VXI bus 54 can easily mount a system structure of the analog measuring section 31 by mounting a module or a printed circuit board of another manufacturer. Note that all units and modules may be manufactured in-house and interfaced with the tester bus 53. The test processor 51 may be provided on the main frame 30. In this case, the test processor 51 is driven by the work station 50.

The main frame 30 is a main component of the semiconductor test apparatus, and mainly includes an analog measuring section 31 and a digital measuring section 41. Each unit and each module of the analog measurement unit 31 in the main frame 30 are connected to a test processor 51 by, for example, a VXI bus 54 and each unit of the digital measurement unit 41 by a tester bus 53 to exchange data. ing. Each will be briefly described.

The analog measuring section 31 includes an arbitrary waveform generator (AWG) 32 for generating an arbitrary analog waveform signal, a digitizer (DGT) 33 for converting an analog signal into a digital signal, It comprises a plurality of analog modules such as a high-level reference voltage generator 34 for generating an arbitrary high-level reference voltage (VRH) and a low-level reference voltage generator 35 for generating an arbitrary low-level reference voltage (VRL). Have been. An event master (EM) 38 controls the operation of the plurality of analog modules and the like.

The event master (EM) 38 generates several kinds of predetermined clock signals from several kinds of clock signals from a clock master (CM: Clock Master) 37, and passes through a plurality of multiplexers arranged in parallel. This is a section that accurately and synchronously controls and outputs the necessary start / stop sequence for each analog-related unit or module in parallel. The analog measuring unit 31 supplies an analog test signal generated by the present apparatus to a DUT (device under test) 22, processes a response signal from the DUT 22, and makes a pass / fail decision to measure the analog section of the DUT 22.

The analog measuring section 31 is provided with a trigger generating means 10 for checking an input / output signal of the DUT 22 using an external measuring instrument 25. The trigger generator 10 includes a 1-bit pattern generator (PG) 11 and a trigger board 12 including a timing generator and a waveform shaper. That is, a 1-bit logic trigger (also referred to as a state trigger) is generated at an arbitrary timing under the control of the test processor 51, transmitted to the test head 20 via the state trigger line 23, and transmitted to the test head 20. 20 can be taken out from the state trigger terminal 24.

The digital measuring unit 41 includes a pattern generator (PG) 44 for generating a logical pattern for testing the DUT 22 and an expected value pattern, a timing generator (TG) 43 for generating a pattern timing, A waveform shaper (FMT) 42 for converting a logic pattern into a test signal to be given to the DUT 22, a pattern comparator (COMP) 45 for comparing a response signal of the DUT 22 with an expected value pattern, and the like are included. Perform measurements in the logic department.

A performance board (PB) 21 is mounted on the test head 20, and a test signal is provided to the DUT 22 to transmit and receive a signal for receiving a response signal to test the DUT 22. The performance board 21 and the analog measuring unit 31 and the digital measuring unit 41 of the main frame 30 are connected by cables. Further, as described above, the test head 20 is provided with the state trigger terminal 24 for checking the input / output signals of the DUT 22 using the external measuring instrument 25, and is connected to the main frame 30 via the state trigger line 23. ing.

FIG. 5 shows a conceptual diagram of an example of measuring the DUT 22 which is a mixed LSI. The test signal from the waveform shaper 42 of the digital measuring section 41 is given to the logic section 17 of the DUT 22, and the response signal is compared with the voltage by the comparator and compared with the expected value pattern by the pattern comparator 45. Pass / fail is determined.

The A / D converter section 18 is given an arbitrary analog waveform from the AWG 32 of the analog measuring section 31 and stores the digital value digitized by the DUT 22 in a DCAP (Data Caputre) 36 which is a buffer memory. Pass / fail is determined later.

In the D / A converter section 19, a high-level reference voltage (VRH) is supplied from the high-level reference voltage generator 34 of the analog measuring section 31 to the H terminal, and a low-level reference voltage generator 35 is supplied from the low-level reference voltage generator 35 to the L terminal. When a low level reference voltage (VRL) is supplied and logic data is supplied from a logic driver pin, the DUT 22 generates an analog signal corresponding to the input logic data signal. The analog signal output from the DUT 22 is digitized by a digitizer (DGT) 33 to determine the quality. The output data of the digitizer 33 may be subjected to data processing by FFT (Fast Fourier Transform) calculation means to determine pass / fail. Some of the DUTs 22 have other departments, but the description is omitted.

[0015]

[Problems to be solved by the invention]

 With the above-described configuration, various mixed LSIs as the DUT 22 are measured and inspected. Incidentally, in the semiconductor test apparatus, a test program is created for each type of DUT 22, and the DUT 22 is tested under conditions suitable for the DUT 22. Since the debug of the test program of the logic section 17 can be logically created, it is relatively easy, and the self-diagnosis of the device can be relatively easily performed automatically by the system diagnostic program.

However, debugging a test program in the analog department and diagnosing a device are not as simple as in the logic department. This is because the progress of development of system LSIs is so rapid that the configuration of the mixed LSI, which is the DUT 22, differs greatly for each product type, and that the characteristics of the analog section differ greatly for each product type. In the testing of the analog division of the semiconductor test equipment, it was not possible to establish a debugging method or a diagnostic method with a greatest common denominator.

According to the conventional method of applying a state trigger to the external measuring instrument 25 to drive the external measuring instrument 25 and check the input / output signals of the DUT 22, the logic section can check synchronously. The department is unable to measure well without synchronization. That is, the burst wave of the clock signal from the event master 38 given to the analog module cannot be observed from the outside. Therefore, when a signal is not correctly output to the DUT 22, it is difficult to find out which setting is wrong.

In view of the above drawbacks, the present invention generates a new trigger for analog measurement as an “event trigger”, applies it to a trigger terminal 26 of an external measuring instrument, checks the input / output signal of the DUT 22, and performs analog measurement. It is intended to improve the debugging efficiency of the test program and to easily perform analog-related diagnosis of the device.

[0019]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention allows a so-called event trigger for analog measurement to be output from the trigger terminal of the test head in addition to the conventional state trigger. The event trigger is a predetermined clock selected from a burst wave of a clock signal supplied from the event master to each analog-related unit or module. In this specification, the event trigger is referred to as an "event trigger". I will say.

The event trigger is transmitted to the test head and output from the trigger terminal of the test head to the trigger terminal of an external measuring instrument so that the input / output signal of the DUT can be checked using the external measuring instrument. I do. Therefore, the trigger input to the trigger terminal of the external measuring instrument is completely synchronized with the operation of the analog module, enabling the test program for analog measurement to be debugged and making it easy to diagnose analog-related operations. Become.

As the event trigger to be taken out from the event master, the first or several clock signals of the burst wave of the clock signal are selected, and a trigger signal is generated by designating it on a test program. Since the external measuring instrument starts measurement from that point, use this event trigger to drive the measurement of the external measuring instrument and check the signal at the input terminal of the DUT in the analog section of the DUT. Because it is completely synchronized with the signal, it is easy to debug an analog test program. Furthermore, when the signal at the output terminal of the DUT is checked, the output waveform of the DUT is observed, which also facilitates debugging of the conditions of the test program.

This event trigger is supplied from the test head to an external trigger terminal of an external measuring instrument. There are two ways to do that. The first method is to provide an event trigger line in parallel with the conventional state trigger line, provide a new event trigger terminal, and supply the event trigger to an external measuring instrument. The measurer has the advantage that measurement can be performed using the state trigger terminal and the event trigger terminal separately.

The second is a method in which an event trigger is interrupted after the trigger board of the conventional state trigger. The means for interrupting may be an OR circuit (OR gate) or an AND circuit (AND gate). In any case, it is necessary to appropriately describe the trigger generation program of the analog measurement test program. The measurer only needs to receive one of the trigger signals according to the program described in common from one conventional state trigger terminal. Next, the configuration of the present invention will be described.

The first device is a basic device. In other words, the test processor controls the entire device, and is a semiconductor test device that has an analog measurement unit. A predetermined clock is generated from the burst wave of the clock signal generated by the event master of the analog measurement unit and supplied to the analog module. A semiconductor test apparatus having an event trigger terminal for selecting a signal to be used as an event trigger, transmitting the event trigger to a test head, and supplying the test head to an external measuring instrument.

The second device is a device that is effective for practical use. In other words, the test processor controls the entire device, and is a semiconductor test device having an analog measurement unit. Selects a clock signal as an event trigger, interrupts the event trigger with the state trigger signal on the trigger board, transmits it to the test head, and supplies the test head with the state trigger or event trigger to an external instrument This is a semiconductor test apparatus having a trigger terminal shared by both a state trigger and an event trigger.

[0026]

[Embodiment of the invention]

 An embodiment of the invention will be described based on an example with reference to the drawings. Fig. 1 is a block diagram of one embodiment of the first invention, Fig. 2 is a block diagram of another embodiment of the second invention, and Fig. 3 is a schematic external view of checking an apparatus using an external measuring instrument. . First, FIG. 1 will be described.

In the configuration diagram of FIG. 1, an event trigger is extracted from the event master EM 38 of the analog measuring section 31 and is sent to the test head 20 via the event trigger line 14 in parallel with the conventional state trigger line 23. Transmitting. The test head 20 can extract an event trigger signal from the event trigger terminal 15. The external measuring device 25 drives the external measuring device 25 by inputting an event trigger from the event trigger terminal 15 to the trigger terminal 26 of the external measuring device. The input / output signal of the analog-related input terminal or the output terminal of the DUT 22 is input to the measurement terminal 27 of the external measuring instrument, and the signal is checked.

As described above, the event trigger is a trigger signal obtained by selecting a predetermined clock signal by a multiplexer from a burst wave of a clock signal generated by the event master 38 and supplied to an analog module, for example, the AWG 32 or the DGT 33. It is. Therefore, it is an event trigger that is completely synchronized with the clock signal applied to the analog module.

A predetermined clock signal can be easily selected from a burst wave of the clock signal by adding a selection symbol to the test program. The clock signal to be selected from the burst wave, that is, the event trigger, may be the first clock signal of the burst wave or the clock signal of several bursts. The point is to select a clock signal at a position where debugging of the test program can be facilitated. This is the first device. Other operations of the apparatus are the same as those of the conventional apparatus shown in FIG.

FIG. 2 is a configuration diagram of another embodiment. The difference from FIG. 1 is that the event trigger line 14 for transmitting the event trigger from the main frame 30 to the test head 20 is shared with the conventional state trigger line 23. Therefore, an interrupt circuit 13 is provided at the subsequent stage of the conventional trigger board 12, and an event trigger from the event master 38 is interrupted to the conventional state trigger line 23. The interrupt circuit 13 may be a logical sum circuit as shown in the figure, or may be a logical product circuit.

When the state trigger line 23 is used by both the state trigger and the event trigger, there is a problem that both triggers occur simultaneously. This can be prevented by checking the test program, because both the state trigger and the event trigger are generated in the test program description. Other operations are the same as in FIG. 1 of the first invention. This is the second device.

FIG. 3 is an external view in which input / output signals of the DUT 22 are checked using the external measuring device 25. The external measuring instrument 25 takes out an event trigger or a state trigger from the state trigger terminal 24 of the test head 20, inputs the event trigger or the state trigger to the trigger terminal 26 of the external measuring instrument, drives it, and outputs the input signal or output signal of the DUT 22. The input / output signal of the DUT 22 is checked by inputting the signal to the measurement terminal 27 of the external measuring instrument.

[0033]

[Effect of the invention]

 As described above in detail, in the conventional semiconductor test apparatus, when the input / output signal of the DUT 22 is checked using the external measuring instrument 25, the trigger signal is only the state trigger. As described above, the state trigger is generated by the trigger PG 11 of the trigger generation means 10. Therefore, the logic circuit check could be easily checked because it can be synchronized with the clock of the operation of the device, but could not be synchronized in analog relations.

In particular, since the burst wave of the clock signal supplied from the event master 38 to the analog module cannot be observed from the outside, even when the correct signal is not output to the DUT 22, it is possible to determine where the setting error exists. It was difficult to find out.

According to the present invention, a predetermined clock signal is selected from a burst wave of a clock signal generated by the event master 38 and applied to the analog module, and is selected as an event trigger. The event trigger is transmitted to the test head 20. Then, the external measuring device 25 is driven as an external trigger of the external measuring device 25.

Therefore, the analog input / output signal given to the DUT 22 by the semiconductor test apparatus is synchronized with the event trigger, and the measurement can be performed in synchronization with the analog section input / output signal. Therefore, the debugging efficiency of the test program for analog measurement has increased, and the diagnosis of the device has become easier. This device has a great technical effect when implemented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a schematic external view of a semiconductor test apparatus having an analog measuring unit, and is an explanatory diagram for checking an analog signal waveform and signals related to analog measurement using an external measuring instrument.

FIG. 3 is a schematic block diagram of a conventional semiconductor test apparatus having an analog measuring unit.

FIG. 4 is a conceptual diagram for testing a mixed LSI that is a DUT 22.

FIG. 5 is a conceptual diagram illustrating an example of measuring a DUT 22, which is a mixed LSI.

[Explanation of symbols]

Reference Signs List 10 trigger generating means 11 trigger PG 12 trigger board 13 interrupt circuit 14 event trigger line 15 event trigger terminal 17 logic section 18 A / D converter section 19 D / A converter section 20 test head (TH) 21 performance board ( PB) 22 DUT (device under test) 23 state trigger line 24 state trigger terminal 25 external measuring instrument 26 external measuring instrument trigger terminal 27 external measuring instrument measuring terminal 30 mainframe (MF) 31 analog measuring section 32 arbitrary waveform Generator (AWG: Arbitrary Waveform)
Generator) 33 Digitizer (DGT) 34 High-level reference voltage generator 35 Low-level reference voltage generator 36 Data memory (DCAP: Data Capture) 37 Clock master (CM) 38 Event master (EM) 41 Digital measurement unit 42 Waveform Shaper (FMT) 43 Timing generator (TG) 44 Pattern generator (PG) 45 Pattern comparator (COMP) 46 Fail memory (FM) 50 Work station (EWS) 51 Test processor 52 Display unit 53 Tester bus 54 VXI bus

Claims (2)

[Utility model registration claims] 1. A semiconductor test apparatus having an analog measuring section, wherein a test processor controls the entire apparatus, and a predetermined clock signal is generated from a burst wave of a clock signal generated by an event master of the analog measuring section and supplied to an analog module. And an event trigger terminal for transmitting the event trigger to a test head and supplying the event trigger to an external measuring instrument by using the test head. 2. A semiconductor test apparatus having an analog measuring unit and a state trigger terminal by controlling the entire apparatus by a test processor, wherein a burst signal of a clock signal generated by an event master of the analog measuring unit and supplied to an analog module is obtained. Selects a predetermined clock signal as an event trigger, interrupts the event trigger with the state trigger signal of the trigger board, transmits it to the test head, and externally measures the state trigger or event trigger with the test head A semiconductor test apparatus comprising a trigger terminal shared by a state trigger and an event trigger to be supplied to a tester.