JP3067850U - Semiconductor test equipment - Google Patents

Abstract

(57) [Summary] A semiconductor test apparatus capable of adjusting a skew between a logic clock and a sampling pulse for an analog test when performing an analog test synchronized with a logic clock. SOLUTION: This is a semiconductor testing device having an analog measuring unit by controlling the entire device with a test processor,
A state trigger generating means for generating a pulse signal;
A switch for connecting a pulse signal transmitted through the state-trigger transmission line to a D / A output transmission line in a test head; and a pulse signal input via the switch and the D / A output transmission line to an event master. A digitizer that is transmitted from the A / D converter with a sampling pulse and
The pulse signal of the state trigger generating means is branched and applied to the event master, and the pulse signal is delayed to AWG
Alternatively, the variable delay circuit includes a variable delay circuit serving as a sampling pulse of the digitizer, and a control unit that changes the delay amount of the variable delay circuit and matches the input pulse signal with the rising edge of the sampling pulse.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 The present invention relates to a semiconductor test apparatus having an analog measurement unit for testing an analog LSI (large-scale integrated circuit) or a mixed LSI, for example, a DUT having a D / A converter (digital / analog converter). Semiconductor test equipment that can adjust the phase difference between the response signal of the logical data clock given to the device under test and the analog clock given to the analog module from the event master of the analog measurement section, that is, the skew to a minimum. About.

Here, a phase difference, that is, a skew will be briefly described. As shown in FIG. 4A, a phase difference, that is, a time difference t occurs when the waveform of the video sampling clock rises in FIG. 4B with respect to the rise of the standard timing clock. This time difference t is called skew. In this specification, the time difference t between the reference clock signal and the clock signal of interest is referred to as skew. This skew may occur in a leading (+) direction and a lagging (-) direction with respect to the reference clock signal.

[0003]

[Prior art]

 The development of semiconductor LSI has been remarkable, and it was previously classified into logic LSI, memory LSI, analog LSI, etc. according to the function of the LSI. Some LSIs have been integrated. For example, a one-chip television LSI, audio LSI, communication LSI MODEM, CODEC, etc. can be said to be typical "mixed LSI" devices. In other words, a mixed LSI is an LSI in which an analog section such as an A / D converter and a D / A converter and a memory section are mixed in addition to a logic section.

There is a mixed semiconductor test apparatus for testing the above-mentioned mixed LSI. There is also an analog semiconductor test apparatus for testing only an analog LSI. Furthermore, recently, a comprehensive semiconductor test device equipped with a section for testing analog circuits has also been developed for digital semiconductor test devices. In this specification, these are collectively referred to as “semiconductor test equipment”. First, a conventional so-called mixed semiconductor test apparatus will be described.

FIG. 2 is a schematic block diagram of a conventional semiconductor test apparatus, FIG. 3 is a conceptual diagram for measuring a DUT 22 which is a mixed LSI, and FIG. 4 is a diagram showing two clocks called so-called skew. The figure explaining a phase difference is shown. This will be described mainly with reference to FIG. The semiconductor test apparatus is roughly divided into a work station (EWS) 50, a main frame (MF) 30, and a test head (TH) 20.

The work station 50 is operated by an operator, and has a test processor 51, a display unit 52, and input / output means such as a keyboard (not shown). The test processor 51 controls the entire apparatus, and supplies a control signal to each unit via the tester bus 53 and the VXI bus 54. The VXI bus 54 is a system bus for modular measuring instruments, which is being standardized in the United States. The system bus was introduced by combining modules and printed circuit boards of different manufacturers to make the system of the analog measuring unit 31 easy. It is because it can be constituted. Therefore, if all the units and modules are made in-house, the tester bus 53 may be used instead of the necessary bus. The test processor 51 may be provided on the main frame 30. At this time, the test processor 51 is driven by the work station 50.

The main frame 30 is a main component of the semiconductor test apparatus, and mainly includes an analog measuring section 31 and a digital measuring section 41. Each unit and each module of the analog measuring unit 31 in the main frame 30 are connected to a test processor 51 by, for example, a VXI bus 54 and each unit of the digital measuring unit 41 by a tester bus 53. We give and receive. Each will be briefly described.

The analog measuring unit 31 includes an arbitrary waveform generator (AWG; Arbitrary Waveform Generator) 32 for generating an arbitrary analog waveform signal, a digitizer (DGT) 33 for converting an analog signal into a digital signal, It consists of multiple analog modules such as a high-level reference voltage generator and a low-level reference voltage generator. An event master (EM) 38 controls the operation of the plurality of analog modules and the like.

In this specification, an event master (EM) 38 is a clock signal obtained by directly or dividing a predetermined clock signal from several types of clock signals from a clock master (CM) 37. A number of types of burst waves are generated in parallel, and the necessary start / stop sequences, etc., required in parallel for each analog-related unit and module are accurately controlled through multiple multiplexers installed in parallel. Means the department that outputs. The analog measuring unit 31 supplies an analog test signal generated by the present apparatus to a DUT (device under test) 22, processes a response signal from the DUT 22, and makes a pass / fail decision to measure the analog section of the DUT 22.

The digital measuring unit 41 includes a pattern generator (PG) 44 for generating a logical pattern for testing the DUT 22 and an expected value pattern, a timing generator (TG) 43 for generating a pattern timing, There is a waveform shaper (FMT) 42 for converting a logic pattern into a test signal to be given to the DUT 22. The waveform shaper (FMT) 42 gives logic data to the DUT 22, and compares a response signal from the DUT 22 with an expected value pattern. 45, etc., and mainly measures the logic section of the DUT 22.

A performance board (PB) 21 is mounted on the test head 20, and a test signal is provided to the DUT 22 to transmit and receive a signal for receiving a response signal to test the DUT 22. Cables are connected between the performance board 21 and the analog measuring section 31 and the digital measuring section 41 of the main frame 30, respectively.

FIG. 3 shows a schematic configuration diagram of an example of the DUT 22 which is a mixed LSI and a conceptual diagram of an example of testing the same. The test signal from the waveform shaper 42 of the digital measuring section 41 is given to the logic section 17 of the DUT 22, and the response signal is compared with the voltage by the comparator and compared with the expected value pattern by the pattern comparator 45. Pass / fail is determined.

The A / D converter section 18 is given an arbitrary analog waveform from the AWG 32 of the analog measuring section 31 and stores the digital value digitized by the DUT 22 in a DCAP (Data Caputre) 36 which is a buffer memory. Pass / fail is determined later.

The D / A converter section 19 is provided with logical data from the waveform shaper 42 of the digital measuring section 41, and the DUT 22 generates an analog signal corresponding to the input logical data signal. An analog signal generated and output from the DUT 22 is transmitted to a digitizer (DGT) 33 of the analog measuring section 31 and digitized by the digitizer 33 to determine whether the signal is good or bad. The output data of the digitizer 33 may be subjected to data processing by FFT (Fast Fourier Transform) calculation means to determine pass / fail. Some DUTs 22 have other departments, but their description is omitted.

A so-called mixed semiconductor test apparatus further includes a state trigger generating means for supplying a state trigger (State Tigger) for an external measuring instrument to be applied to an external trigger terminal of a spectrum analyzer or the like as shown in FIG. 10 are provided. The state trigger generating means 10 is connected to the tester bus 53 and can generate a state trigger clock signal in synchronization with the clock signal of the digital measuring section 41. Then, the data is supplied to the test head 20 via a state trigger transmission line, and supplied to an external measuring instrument from the state trigger terminal of the test head 20.

As shown in FIG. 3, for example, the timing of the logical data for generating the analog signal of the D / A converter section 19 of the DUT 22 is given by the clock of the digital measuring unit 41. The analog signal as the response signal is supplied to the digitizer 33 via the transmission line 49 of the D / A output. The timing of a sampling clock and the like given to the digitizer 33 for analyzing the analog signal is given from the event master 38 of the analog measuring section 31 via the sampling pulse transmission line 48. Therefore, the timings of the two in the DGT 33 are not synchronized, and the skew between the two is about 70 ns (nanosecond) to about 80 ns.

[0017]

[Problems to be solved by the invention]

 With the conventional configuration of FIG. 2, in the analog frequency band related to audio of about 2 KHz in the D / A converter section 19, even if the digital data is analyzed by the DGT 33 for audio and the digital data is analyzed, the audio signal is not changed. Since the skew variation time is very small compared to the cycle time, analog tests can be performed without any problem.

However, in the case of the DGT 33 for video having a high frequency of several tens of MHz or more, the order of the cycle time and the skew variation time of the analog signal of the video signal is gradually approximated. This is not preferred because of variations in the quality. In a semiconductor test apparatus, when an analog test synchronized with a digital test clock is performed for both audio signals and video signals, it is desired that the skew time is at least a fixed skew time ± several ns.

A first object of the present invention is to provide a device for greatly improving the skew between an input signal and a sampling pulse in a digitizer 33 when testing a D / A converter synchronized with a digital test clock. To provide. A second object of the present invention is to output an analog signal from an arbitrary waveform generator (AWG) 32 of an analog measuring section to the DUT 22 and provide a response signal to the digitizer 33. It is an object of the present invention to provide a device for greatly improving the skew of the sampling pulse supplied to the DUT 33 and the response signal from the DUT.

[0020]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention provides a circuit for adjusting the skew time to a constant value before testing the DUT 22, using a transmission line of a state trigger for an external measuring instrument. The distance between the main frame 30 and the test head 20 is several meters or more. Accordingly, logic data is supplied from the waveform shaper 42 of the main frame 30 to the D / A converter section 19 of the DUT 22, for example, via the logical data transmission path 47, and an analog signal as a response signal is converted to a D / A output. There is a delay time before the signal is given to the digitizer 33 via the transmission line 49. In addition, there is a delay time before the arbitrary waveform generated by the AWG 32 is applied to the DUT and its response signal is applied to the digitizer 33.

Therefore, in order to realize the first object, a pulse signal is generated by the state trigger generation means 10 and transmitted to the test head 20 (including the performance board 21) through the state trigger transmission line. Then, the pulse signal is connected to the transmission line 49 of the D / A output via the first switch and supplied to the digitizer 33. In other words, the delay time for giving the logical data from the waveform shaper 42 to the DUT 22 to the digitizer 33 via the D / A output transmission line 49 and the pulse signal from the state / trigger generating means 10 to the test head 20 Then, the delay time between the connection to the transmission line 49 of the D / A output via the first switch and the application to the digitizer 33 is made equal or a constant skew time.

On the other hand, the pulse signal generated by the state trigger generating means 10 is branched and applied to the event master 38, and the pulse signal converted into a sampling pulse through the first variable delay circuit is transmitted to the sampling pulse transmission line 48. Through the digitizer 33. Prior to the test of the DUT 22, the pulse signal of the state trigger transmitted from the test head 20 via the transmission line 49 of the D / A output, and the pulse signal transmitted from the event master 38 via the transmission line 48 of the sampling pulse. Compare with the sampled pulse.

The comparison between the two pulses uses the pulse signal transmitted via the D / A output transmission line 49 as a reference pulse, and the sampling pulse adjusts the delay amount of the first variable delay circuit of the event master 38. Meanwhile, the delay amount at the same point of rising is determined and set. To find the same point of rising, the phase of the sampling pulse is changed while gradually changing the delay amount of the first variable delay circuit, and the point at which the reference pulse changes from "0" to "1" is obtained. Good.

In order to realize the invention of the second object, first, the invention of the first object is realized, the phase of the sampling pulse is fixed, and then the state pulse is generated by the state trigger generation means 10 and branched to generate an event. The pulse signal supplied to the master 38 is used as a clock signal supplied to the AWG 32 through the second variable delay circuit. A pulse signal is generated by the clock signal, transmitted to the test head 20 via the AWG output transmission line 46, connected to the D / A output transmission line 49 by the second switch, and transmitted to the digitizer 33.

The digitizer 33 transmits the D / A output while gradually changing the delay amount of the second delay circuit based on the sampling pulse transmitted from the event master 38 via the sampling pulse transmission line 48. The phase of the pulse signal transmitted from the path 49 to the digitizer 33 is changed, and the delay amount at the time when the pulse signal changes from “0” to “1” is obtained and set.

Next, the configuration of the present invention will be described. The first invention is a semiconductor test apparatus capable of adjusting a skew between an input signal transmitted from a test head 20 and input to a digitizer and a sampling pulse of the digitizer. In other words, a semiconductor test device that controls the entire device with a test processor, has an analog measurement unit, generates a pulse signal, transmits it to the test head via a state trigger transmission line, and sends a pulse signal to the state trigger terminal And a first switch for connecting a pulse signal of the state trigger transmission line to a transmission line of the D / A output in the test head, and a transmission line of the first switch and the D / A output. A pulse signal transmitted from the event master, and converts the pulse signal input from the event master into analog-to-digital conversion with a sampling pulse. In the event master, which delays the signal by a specified amount and turns it into an AWG or digitizer sampling pulse The first variable delay circuit provided and the delay amount of the first delay circuit are changed to change the phase of the sampling pulse, and the pulse signal input via the D / A output transmission line and the rising of the sampling pulse are changed. This is a semiconductor test apparatus which includes a control unit for matching, and can adjust a skew between an input pulse and a sampling pulse in a digitizer before testing a DUT.

The second invention is a semiconductor test apparatus capable of adjusting a skew between a clock signal applied to an arbitrary waveform generator 32 of an analog measuring section 31 and a sampling pulse applied to a digitizer 33. In other words, in addition to the semiconductor test device of the first invention, the pulse signal generated by the state trigger generating means is branched, and the pulse signal given to the event master is delayed by a predetermined amount so as to be synchronized with the clock signal of the arbitrary waveform generator A second variable delay circuit provided in the event master that performs the operation, and an AWG output transmission path for outputting an output signal of a square wave signal generated by the arbitrary waveform generator using the clock signal delayed by the second variable delay circuit. A second switch connected to the D / A output transmission line in the test head, and a square wave signal transmitted to the digitizer through the second switch and the D / A output transmission line. A control unit that changes the amount of delay of the second delay circuit to change the phase of the rectangular wave signal, and matches the rising edge of the sampling pulse given to the digitizer. A semiconductor testing device capable of adjusting the skew of the sampling pulse to be supplied to the clock signal and the digitizer to be applied to arbitrary waveform generator prior to testing.

[0028]

[Embodiment of the invention]

 An embodiment of the invention will be described based on an example with reference to the drawings. FIG. 1 shows a configuration diagram of an embodiment of the present invention. The difference between the devised configuration diagram of FIG. 1 and the conventional configuration diagram of FIG. 2 is that in the test head 20 including the performance board 21, the state / trigger transmission path and the D / A output transmission path 49 are connected. The first switch 5 includes a second switch 6 that connects the transmission line 46 for AWG output and the transmission line 49 for D / A output. A first variable delay circuit 7 and a second variable delay circuit 8 for branching the pulse signal generated by the state trigger generating means 10 and providing the branched signal to the event master 38 for delaying the pulse signal; The output signal of the first variable delay circuit 7 is provided to the digitizer 33 as a sampling pulse, and the output signal of the second variable delay circuit 8 is provided to the AWG 32 as a clock signal.

Since the state trigger generating means 10 is composed of PG11 or the like for one bit of the digital measuring section 41, it can generate a pulse in synchronization with the clock of the logical data of the digital measuring section 41. . The length of the state-triggered transmission line for transmitting the generated pulse to the test head 20 is almost the same as the length of the logical data transmission line 47 for transmitting the logical data from the FMT 42 to the test head 20. Assume that the times are about the same.

Therefore, prior to the test of the DUT 22, the pulse signal generated by the state trigger generating means 10 is transmitted to the test head 20 via the state trigger transmission line, and the D / A output of the D / A output is transmitted through the first switch 5. It is connected to the transmission line 49 and transmitted to the digitizer 33 via the transmission line 49 of the D / A output.

On the other hand, the pulse signal generated by the state trigger generating means 10 is branched and applied to the event master 38 of the analog measuring section 31 to sample the pulse signal obtained by the first variable delay circuit 7. The pulse is given to the digitizer 33. The input pulse changes from “0” to “1” by measuring the input pulse from the transmission line 49 of the D / A output while changing the phase of the sampling pulse in the first variable delay circuit 7. The delay amount of the first variable delay circuit 7 at the phase point minimizes the skew. This is the first device.

Next, as in the case of the first invention, the timing of the clock signal applied to the AWG 32 is adjusted so that the skew between the pulse signal input to the digitizer 33 and the sampling pulse is minimized. That is, the pulse signal generated by the state trigger generating means 10 is branched, and the pulse signal supplied to the event master 38 of the analog measuring section 31 is used as a clock signal supplied to the AWG 32 via the second variable delay circuit 8. Using this clock signal, the AWG 32 generates and outputs a pulse signal.

The output signal of the AWG 32 is transmitted to the test head 20 via the AWG output transmission line 46, and connected to the D / A output transmission line 49 via the second switch 6 by the test head 20, and the D / A The output is provided to the digitizer 33 via a transmission line 49. Since the timing of the sampling pulse given from the event master 38 to the digitizer 33 has already been adjusted, the timing is measured while changing the timing of the clock signal given to the AWG 32 by adjusting the second variable delay circuit 8. The delay amount of the second variable delay circuit 8 at the point where the pulse signal output from the AWG 32 and input to the digitizer 33 from the D / A output transmission line 49 changes from “0” to “1” is skipped. This is the value that minimizes the queue. This is the second device.

[0034]

[Effect of the invention]

 As described above in detail, it is possible to adjust the skew in the digitizer 33, which cannot be performed by the conventional semiconductor test apparatus. That is, in the present invention, the skew between the signal input to the digitizer 33 and the sampling pulse can be adjusted to the minimum by reciprocating the transmission path of several meters or more from the main frame 30 to the test head 20. According to the experiment, the skew time can be suppressed to ± 1 ns.

Therefore, in the test of the video signal as well as the test of the audio signal, there is no variation in the test data in different semiconductor test devices, and the reproducibility is improved and the reliability is improved. In practical use, the technical effect is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an example of a conventional configuration diagram.

FIG. 3 is a conceptual diagram for testing a mixed LSI that is a DUT 22.

FIG. 4 is an explanatory diagram illustrating a skew of the present apparatus.

[Explanation of symbols]

Reference Signs List 5 first switch 6 second switch 7 first variable delay circuit 8 second variable delay circuit 10 state trigger generating means 11 trigger PG 13 digital comparator (COMP) 17 logic section 18 A / D converter section 19 D / A converter Section 20 Test Head (TH) 21 Performance Board (PB) 22 DUT (Device Under Test) 30 Mainframe (MF) 31 Analog Measurement Unit 32 Arbitrary Waveform (AWG)
Generator) 33 Digitizer (DGT; Digitizer) 36 Data memory (DCAP; Data Capture) 37 Clock master (CM) 38 Event master (EM) 41 Digital measurement unit 42 Waveform shaper (FMT) 43 Timing generator (TG) 44 Pattern Generator (PG) 45 Pattern Comparator (COMP) 46 AWG Output Transmission Line 47 Logical Data Transmission Line 48 Sampling Pulse Transmission Line 49 D / A Output Transmission Line 50 Work Station (EWS) 51 Test Processor (TP) 52 Display 53 Tester bus 54 VXI bus

Claims (2)

[Utility model registration claims] A test processor controls the entire apparatus, generates a pulse signal in a semiconductor test apparatus having an analog measuring unit, transmits the pulse signal to a test head via a state trigger transmission line, and supplies a pulse signal to a state trigger terminal. And a first switch for connecting the pulse signal of the state trigger transmission line to a transmission path of the D / A output in the test head; and a first switch and a transmission path of the D / A output. A digitizer that transmits a pulse signal input from the event master and converts it into an analog-to-digital signal with a sampling pulse. The pulse signal generated by the state trigger generator is branched and applied to the event master, and the pulse signal is supplied to the event master. Event master with AWG or digitizer sampling pulse delayed A variable delay circuit provided in the first and second circuits, and changing the amount of delay of the first delay circuit to change the phase of the sampling pulse, and changing the pulse signal input through the D / A output transmission line and the rising of the sampling pulse. A semiconductor control apparatus comprising: a controller configured to match the skew between the input pulse and the sampling pulse in the digitizer before testing the DUT. 2. An arbitrary waveform generator according to claim 1, wherein the pulse signal generated by the state trigger generating means is branched, and the pulse signal supplied to the event master is delayed by a predetermined time. A second variable delay circuit provided in an event master serving as a clock signal, and an AWG output signal of a square wave signal generated by an arbitrary waveform generator using the clock signal delayed by the second variable delay circuit
A second switch connected to the D / A output transmission line in the test head and transmitted to the digitizer through the second switch and the D / A output transmission line in the test head. A controller that changes the phase of the rectangular wave signal by changing the amount of delay of the rectangular wave signal to change the phase of the rectangular wave signal to match the rising of the sampling pulse given to the digitizer. A skew between a clock signal applied to an arbitrary waveform generator and a sampling pulse applied to a digitizer.