JP3066074U - Semiconductor test equipment - Google Patents

Abstract

(57) [Summary] A semiconductor test apparatus for quickly measuring jitter of a clock signal of a DUT. SOLUTION: This is a semiconductor test apparatus having an analog measuring unit, in which a test processor controls the entire apparatus, and a sampling pulse oscillator oscillating a sampling pulse of (1 / integer) times a clock signal of a DUT; Receiving the sampling pulse,
A variable delay means for delaying a pulse for an arbitrary time, a sampler for sampling a clock signal of a DUT with a delayed sampling pulse, and a delay time of the variable delay means for changing a timing of a sampling pulse; Control means for searching for an edge of a clock signal of a DUT.

Description

[Detailed description of the invention]

[0001]

[Technical field to which the invention belongs]

 This invention is a semiconductor test apparatus having an analog measurement unit for testing an analog LSI (large-scale integrated circuit) or a mixed LSI, and can measure a jitter of a clock used in a DUT (device under test). The present invention relates to a semiconductor test device.

[0002]

[Prior art]

 The development of semiconductor LSI has been remarkable, and it was previously classified into logic LSI, memory LSI, analog LSI, etc. according to the function of the LSI. Some LSIs have been integrated. For example, a one-chip television LSI, audio LSI, communication LSI MODEM, CODEC, etc. can be said to be typical "mixed LSI" devices. In other words, a mixed LSI is an LSI in which an analog section such as an A / D converter and a D / A converter and a memory section are mixed in addition to a logic section.

There is a mixed semiconductor test apparatus for testing the above-mentioned mixed LSI. There is also an analog semiconductor test apparatus for testing only an analog LSI. Furthermore, recently, a comprehensive semiconductor test device equipped with a section for testing analog circuits has also been developed for digital semiconductor test devices. In this specification, these are collectively referred to as “semiconductor test equipment”. First, a conventional so-called mixed semiconductor test apparatus will be described.

FIG. 5 is a schematic block diagram of a conventional semiconductor test apparatus, FIG. 4 is a configuration diagram of an example of a sampling head used in the apparatus, and FIG. 6 is a conceptual view of measuring a DUT 22 as a mixed LSI. FIG. 7 shows a possible explanatory diagram of a method for measuring the jitter of the clock of the DUT. This will be described mainly with reference to FIG. The semiconductor test apparatus is roughly divided into a work station (EWS) 50, a main frame (MF) 30, and a test head (TH) 20.

The work station 50 is operated by an operator and includes a test processor 51, a display unit 52, and input / output means such as a keyboard (not shown). The test processor 51 controls the entire apparatus, and supplies a control signal to each unit via the tester bus 53 and the VXI bus 54. The VXI bus 54 is a system bus for modular measuring instruments, which is being standardized in the United States. The system bus was introduced because the system of the analog measuring unit 31 was constructed by combining modules and printed circuit boards of different manufacturers. This is because it can be easily configured. Therefore, if all units and modules are manufactured in-house, the test bus 53 may be used instead of the necessary bus. The test processor 51 may be provided in the main frame 30, but at this time, the test processor 51 is driven by the work station 50.

The main frame 30 is a main component of the semiconductor test apparatus, and mainly includes an analog measuring section 31 and a digital measuring section 41. Each unit and each module of the analog measurement unit 31 in the main frame 30 are connected to a test processor 51 by, for example, a VXI bus 54 and each unit of the digital measurement unit 41 by a tester bus 53 to exchange data. ing. Each will be briefly described.

The analog measuring section 31 includes an arbitrary waveform generator (AWG) 32 for generating an arbitrary analog waveform signal, a digitizer (DGT) 33 for converting an analog signal into a digital signal, It comprises a plurality of analog modules such as a high-level reference voltage generator 34 for generating an arbitrary high-level reference voltage (VRH) and a low-level reference voltage generator 35 for generating an arbitrary low-level reference voltage (VRL). Have been. An event master (EM) 38 controls the operation of the plurality of analog modules and the like.

In this specification, an event master (EM) 38 is a clock signal obtained by directly or dividing a predetermined clock signal from several types of clock signals from a clock master (CM) 37. A number of types of burst waves are generated in parallel, and the necessary start / stop sequences, etc., required in parallel for each analog-related unit and module are accurately controlled through multiple multiplexers installed in parallel. Means the department that outputs. The analog measuring unit 31 supplies an analog test signal generated by the present apparatus to a DUT (device under test) 22, processes a response signal from the DUT 22, and makes a pass / fail decision to measure the analog section of the DUT 22.

The digital measuring unit 41 includes a pattern generator (PG) 44 for generating a logical pattern for testing the DUT 22 and an expected value pattern, a timing generator (TG) 43 for generating a pattern timing, A waveform shaper (FMT) 42 for converting a logic pattern into a test signal to be given to the DUT 22, a pattern comparator (COMP) 45 for comparing a response signal of the DUT 22 with an expected value pattern, and the like are included. Perform measurements in the logic department.

[0010] A performance board (PB) 21 is mounted on the test head 20, and a test signal is provided to the DUT 22 to transmit and receive a signal for receiving a response signal to test the DUT 22. Cables are connected between the performance board 21 and the analog measuring section 31 and the digital measuring section 41 of the main frame 30, respectively.

FIG. 6 shows a schematic configuration diagram of an example of the DUT 22 which is a mixed LSI and a conceptual diagram of an example of testing the same. The test signal from the waveform shaper 42 of the digital measuring section 41 is given to the logic section 17 of the DUT 22, and the response signal is compared with the voltage by the comparator and compared with the expected value pattern by the pattern comparator 45. Pass / fail is determined.

The A / D converter section 18 is given an arbitrary analog waveform from the AWG 32 of the analog measuring section 31 and stores a digital value digitized by the DUT 22 in a DCAP (Data Caputre) 36 which is a buffer memory. Pass / fail is determined later.

In the D / A converter section 19, a high-level reference voltage (VRH) is supplied from the high-level reference voltage generator 34 of the analog measuring unit 31 to the H terminal, and a low-level reference voltage generator 35 is supplied from the low-level reference voltage generator 35 to the L terminal. When a low-level reference voltage (VRL) is applied and logic data is applied from a logic driver pin, the DUT 22 generates an analog signal corresponding to the input logic data signal. The analog signal output from the DUT 22 is digitized by a digitizer (DGT) 33 to determine the quality.

The semiconductor test apparatus is also provided with a sampling head (SH) 39 for processing a high-frequency signal of several hundred MHz or more from the DUT 22. The high frequency signal is converted into a signal of several MHz or less by the sampling head 39 and sent to the digitizer 33. The output data of the digitizer 33 may be subjected to data processing by an FFT (Fast Fourier Transform) operation means to determine the quality. The sampling head 39 is generally provided on the test head 20, but in this specification, the sampling head 39 is provided on the main frame 30 for explanation.

As described above, the semiconductor LSI which is the DUT 22 has remarkably developed, and is increasingly developed as a system LSI. Therefore, conventionally, test items that are not test items are required. One of them is a measurement item of the jitter of the clock signal generated by the DUT 22. Jitter is a temporal fluctuation of a signal, and a rapid and intermittent change in phase. For example, left and right swings of a signal waveform observed on an oscilloscope.

As shown in FIG. 6, the DUT 22 has a clock generation section 15, which supplies the generated clock signal to another logic section 17, an A / D converter section 18, a D / A converter section 19, and the like. And perform a comprehensive operation while synchronizing. Some recent DUTs 22 have a clock output terminal 16. If the jitter of the DUT 22 is large, a problem such as a malfunction occurs in the system configuration of the electronic device, so that a test is required. The jitter of the clock signal at the clock output terminal 16 is measured by a semiconductor test device.

As a method of measuring the jitter using a semiconductor test apparatus, a method shown in FIG. 7 can be considered. FIG. 7A shows a clock signal of the DUT 22, and the repetition frequency is, for example, 20 MHz. FIG. 7B shows a sampling clock of the semiconductor test apparatus, for example, 2.01 MHz. Although not shown, a sampling pulse is generated at the rising edge of the sampling clock in FIG. 7B, and the phase of the sampling pulse is slightly shifted from the signal under measurement. Samples clock pulse.

To perform sampling, for example, a sampling head shown in FIG. 4 is used. When the sampled signal is applied to the digitizer 33 to obtain data, for example, a clock pulse of the DUT 22 as shown in FIG. 7C is reproduced. The numbers on the waveform in FIG. 7C are the numbers of the sampling points. The period between the edges of this data is a period, and data 6 and data 24 are a period as shown in FIG. Jitter is obtained by comparing periods between edges of a plurality of waveforms.

[0019]

[Problems to be solved by the invention]

 Even with the configuration of the conventional semiconductor test apparatus, the jitter of the clock signal of the DUT 22 can be obtained. However, as described above, when jitter is measured using a sampler with a sampling head and a digitizer, the waveform is reproduced by sampling all the waveforms of the DUT clock signal, which is the signal under measurement, over several periods. There is a need.

[0020] This means that the number of sampling points becomes very large, so that much time is required for this jitter measurement, the efficiency of the overall measurement is reduced, and the test cost is improved. This invention aims to quickly measure the jitter of the clock signal of the DUT with a little additional hardware.

[0021]

[Means for Solving the Problems]

 In order to achieve the above object, the present invention provides a sampling pulse oscillator that oscillates a pulse signal having a frequency that is (1 / integer) times the frequency of the clock signal of the DUT, that is, a frequency that is a fraction of an integer, and a sampling pulse. Delay means for delaying the clock signal by an arbitrary time, a sampler for sampling the clock signal of the DUT with the delayed sampling pulse, and control for changing the delay amount of the variable delay means to search for the edge of the clock signal of the DUT. Means.

[0022] The sampling pulse oscillator is preferably located in a clock source attached to the clock master. This is because the semiconductor test equipment installs and manages a number of main clock oscillators on the clock source attached to the clock master. The frequency of the DUT clock signal is described in specifications, instruction manuals, etc., and is generally known. Therefore, the sampling pulse oscillator may be a synthesizer which can oscillate a pulse with low jitter and oscillate a predetermined frequency (1 / integer) times the DUT clock signal.

The low jitter sampling pulse is provided to the sampler through variable delay means that can delay any time. The variable delay means is preferably provided in an event master which inputs and processes several types of clock signals from the clock master and outputs the required start / stop in parallel to each analog-related module. However, since this sampling pulse requires a low-jitter, high-purity pulse, it is received directly from the sampling pulse oscillator, delayed, and transmitted to the sampler.

Although a sampler may be provided independently, it is common for a semiconductor test apparatus to have a sampling head and a digitizer already installed. Therefore, it is preferable to use both of them as a sampler. Good. The sampler having received the sampling pulse from the variable delay means samples the clock signal from the DUT and processes the data.

The resolution of the above-mentioned variable delay means is determined by the required performance according to the technological level of the times, but it is assumed that the variable delay means can perform variable delay in units of 1 ns (10 ⁻⁹ seconds), for example. The control of the delay time is performed by control means. The control means may be provided in a part of the test processor. The delay time can be arbitrarily varied by control by the test program of the control means.

The control means changes the edge of the sampling pulse to search for the edge of the clock signal of the DUT. For the search, the binary search method of the high-speed search method is preferable. The binary search method is a method in which the target point is determined by comparing the magnitude of a target point with the midpoint of two points sandwiching the point, excluding half the search area, and repeating this process. . Once the edge of the clock signal of the DUT is confirmed, the amount of jitter can be measured by measuring the swing of the subsequent edge based on the amount of delay at that time. Next, the contents of the invention will be described.

The first device is a basic device. In other words, a semiconductor test device having an analog measuring unit, in which the test processor controls the entire device, generates a sampling pulse that oscillates a sampling pulse having a frequency (1 / integer) times the clock signal of the DUT. A pulse oscillator, a variable delay means for receiving the sampling pulse and delaying the sampling pulse for an arbitrary time, a sampler for sampling the clock signal of the DUT with the delayed sampling pulse, and a variable delay means. And a control means for changing the timing of the sampling pulse by changing the delay time and searching for the edge of the clock signal of the DUT.

The second device is a specific device suitable for a conventional design method. In other words, the test processor controls the entire apparatus, and is a semiconductor test apparatus having an analog measuring unit. The sampling pulse oscillator oscillates a sampling pulse having a frequency (1 / integer) times the clock signal of the DUT. A master having variable delay means for receiving a sampling pulse from the clock master and delaying the sampling pulse for an arbitrary time; and a delayed sampling from the event master. A sampling head that samples the clock signal of the DUT with pulses, a digitizer that receives and digitizes the sampled clock signal of the DUT from the sampling head, and changes the delay time of the variable delay means of the event master. , DUT clock signal And a control means for searching for an edge of the DUT and measuring the jitter of the clock signal of the DUT.

[0029]

[Embodiment of the invention]

 An embodiment of the invention will be described based on an example with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a semiconductor test apparatus according to the present invention, FIG. 2 is a block diagram of an example of a variable delay device used in the present invention, and FIG. 3 is a diagram of a clock signal of a DUT according to the present invention. FIG. 4 shows an explanatory diagram for searching for an edge, and FIG. 4 shows a configuration diagram of an example of a sampling head.

Description will be made using numerical values. For example, the repetition frequency of the DUT clock signal is 10 MHz, that is, the period is 0.1 μs, and the repetition frequency of the sampling pulse is 1 MHz, that is, the period is 1 μs. This means that the sampling pulse is oscillated at (1/10) times the frequency of the DUT clock signal. The two are not in phase. In order to synchronize them, the rising edges of both, that is, the phases of the sampling pulses are delayed and changed with a resolution of, for example, 1 ns, and are made to coincide. Based on the delay time at the time of the first coincidence and the voltage level at that time, the delay time is kept constant, and the maximum voltage level change thereafter is obtained. The maximum change amount of the voltage level is converted into a time change amount, and is referred to as jitter.

The simplest means for converting a voltage level change into a time change will be described. FIG. 7C shows the waveform of the clock signal of the DUT 22. The voltage level at which the rising edge coincides with the sampling pulse is defined as the voltage level at point 6 in FIG. 7C. When a sampling pulse with low jitter is generated at regular intervals and the voltage level of the clock signal of the DUT in which jitter occurs is measured, the voltage level changes every measurement because the clock signal swings right and left.

The maximum change amount of the measured voltage level is defined as Y. Let X be the amount of jitter that swings left and right. Assuming that the rising waveform of the clock signal of the DUT is a straight line, the angle is θ. Then, the formula of (Y / X) = tanθ is established. Therefore, X = (Y / tan θ), and the jitter amount X can be obtained by measuring the maximum change amount Y of the voltage level.

FIG. 1 is a block diagram of an embodiment of the present invention. Although not shown, the clock master 37 processes clock signals from a plurality of attached clock sources. The clock source includes a synthesizer capable of oscillating an arbitrary frequency. This synthesizer generates a low jitter sampling pulse of 1 MHz, which is (1 / integer) times the repetition frequency of the clock signal of the DUT, which is one tenth of the above value. The clock master 37 transmits the 1 MHz low jitter sampling pulse to the event master 38 as it is.

Even in the event master 38, the data is directly input to the newly provided variable delay means 5 without any particular processing, and is output to the sampling head 39 so that it can be arbitrarily delayed in, for example, 1 ns. In other words, in the event master 38 and the clock master 37, if the sampling clock is processed by dividing or passing through a multiplexer, a new jitter is generated. It is configured so that the pulse can be output as it is.

FIG. 2 is a configuration diagram of an example of the variable delay means 5 newly provided in the event master 38. Sampling pulses are input from the input terminal 8 _1, outputs from an output terminal _82. The delay element 7i (i = 1 to n) delays a fixed time in, for example, a cascade of inverters. For example, if it is a variable delay means 5 of 1ns units, delay element ₇₁ is set to 1ns delay time, the delay element 7 ₂ and 2 ns, the delay element 7 ₃ and 4 ns, the delay element 7n is 2 ^n-1 ns To perform analog delay. Reference numeral 6i (i = 1 to n) denotes a selector for directly passing a sampling pulse or passing a signal delayed by a delay element 7i. The selector 6i is controlled by a selection signal from the register 9.

The register 9 inputs a selection signal from the data input terminal 10, latches the selection signal with a clock signal from the clock terminal 12 when the enable signal from the enable terminal 11 is output, and outputs the selection signal to the selector 6 i. .

FIG. 3 is an explanatory diagram of an example of searching for the edge of the clock signal of the DUT, and the edge is searched by the binary search method with the edge of the clock signal of the DUT interposed therebetween. FIG. 4 is a configuration diagram of an example of the sampling head 39 that can be used in the present invention. The diode bridge 40 turns on only when a sampling pulse from the clock master 37 is input. At this time, the level of the DUT clock signal, which is an input signal, is charged to the storage capacitor Ch and output to the digitizer 33 via the buffer amplifier.

The digitizer 33 digitizes the analog signal, processes the data, and searches for a match between the edge of the clock signal of the DUT and the edge of the sampling pulse. Based on the delay time and the voltage level of the variable delay means 5 at the time of the first coincidence, the amount of change in the voltage level due to the swing of the edge of the clock signal of the DUT is sampled and measured. Then, the jitter amount of the clock signal of the DUT is measured.

[0039]

[Effect of the invention]

 As described in detail above, to measure the jitter of the clock signal of the DUT, the conventional method digitizes the clock signal of the DUT, reproduces the waveform, calculates the period, and calculates the clock signal of a plurality of DUTs. The only difference was the measurement of the period difference and the runout. Therefore, the number of points to be measured is very large, and the measurement time becomes very long.

The present invention aims to quickly measure the jitter of a DUT clock signal, and for that purpose, generates a sampling pulse having a frequency (1 / integer) times the frequency of a known DUT clock signal. The edge of the clock signal of the DUT is searched while the sampling pulse is delayed by the variable delay means 5. The jitter of this edge is measured and the jitter is measured. Therefore, the measurement time is greatly reduced and the number of calculations is reduced. The technical effect of this invention is great.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a semiconductor test apparatus according to the present invention.

FIG. 2 is a configuration diagram of an example of a variable delay unit 5 used in the present invention.

FIG. 3 is a diagram illustrating an example of searching for an edge of a clock signal of a DUT according to the present invention;

FIG. 4 shows a sampling circuit used in the present invention and the conventional configuration.
FIG. 3 is a configuration diagram of an example of a head 39.

FIG. 5 is a schematic configuration diagram of an example of a conventional semiconductor test device.

FIG. 6 is a schematic configuration diagram of an example of a DUT 22, which is a mixed LSI, and a conceptual diagram of an example of testing the same.

FIG. 7 is a possible explanatory diagram of a method of measuring a jitter of a clock of a DUT 22 in a conventional semiconductor test apparatus.

[Explanation of symbols]

 Reference Signs List 5 variable delay means 6i (i = 1 to n) selector 7i (i = 1 to n) delay element 9 register 10 data input terminal 11 enable terminal 12 clock terminal 15 clock generation section 16 clock output terminal 17 logic section 18 A / D Converter section 19 D / A converter section 20 Test head (TH) 21 Performance board (PB) 22 DUT (device under test) 30 Main frame (MF) 31 Analog measuring section 32 Arbitrary waveform generator (AWG) 33 Digitizer (DGT) 34 High-level reference voltage generator 35 Low-level reference voltage generator 36 Data memory (DCAP) 37 Clock master (CM) 38 Event master (EM) 39 Sampling head (SH) 40 Diode bridge 41 Digital measuring unit 42Waveform shaper (FMT) 43 Timing generator (TG) 44 Pattern generator (PG) 45 Pattern comparator (COMP) 46 Fail memory (FM) 50 Work station (EWS) 51 Test processor (TP) 52 Display unit 53 Tester bus 54 VXI bus Y Maximum change in voltage level X Jitter amount X θ Angle of rising waveform of clock signal

Claims (2)

[Utility model registration claims] 1. A sampling pulse oscillator for controlling a whole apparatus by a test processor and oscillating a sampling pulse having a frequency (1 / integer) times the frequency of a clock signal of a DUT in a semiconductor test apparatus having an analog measuring unit. A variable delay means for receiving the sampling pulse and delaying the sampling pulse for an arbitrary time; a sampler for sampling a clock signal of the DUT with the delayed sampling pulse; and changing a delay time of the variable delay means. Control means for changing the timing of the sampling pulse to search for the edge of the clock signal of the DUT. 2. A sampling pulse oscillator for controlling a whole apparatus by a test processor and oscillating a sampling pulse having a frequency (1 / integer) times the frequency of a clock signal of a DUT in a semiconductor test apparatus having an analog measuring unit. Receiving a sampling pulse from the clock master having
An event master having variable delay means for delaying the sampling pulse by an arbitrary time; a sampling head for sampling a DUT clock signal with a delayed sampling pulse from the event master; and a sampling head. Sampled DUT
A digitizer that receives the clock signal of digitizer and digitizes it.
And a control means for searching for an edge of the clock signal of (1), wherein the jitter of the clock signal of the DUT is measured.