JPS6220448A - ビツトサンプル方式 - Google Patents
ビツトサンプル方式Info
- Publication number
- JPS6220448A JPS6220448A JP60159802A JP15980285A JPS6220448A JP S6220448 A JPS6220448 A JP S6220448A JP 60159802 A JP60159802 A JP 60159802A JP 15980285 A JP15980285 A JP 15980285A JP S6220448 A JPS6220448 A JP S6220448A
- Authority
- JP
- Japan
- Prior art keywords
- sample
- control circuit
- line connection
- line
- spc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Dc Digital Transmission (AREA)
- Communication Control (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60159802A JPS6220448A (ja) | 1985-07-19 | 1985-07-19 | ビツトサンプル方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60159802A JPS6220448A (ja) | 1985-07-19 | 1985-07-19 | ビツトサンプル方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6220448A true JPS6220448A (ja) | 1987-01-29 |
| JPH0368587B2 JPH0368587B2 (cg-RX-API-DMAC7.html) | 1991-10-29 |
Family
ID=15701573
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60159802A Granted JPS6220448A (ja) | 1985-07-19 | 1985-07-19 | ビツトサンプル方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6220448A (cg-RX-API-DMAC7.html) |
-
1985
- 1985-07-19 JP JP60159802A patent/JPS6220448A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0368587B2 (cg-RX-API-DMAC7.html) | 1991-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5073853A (en) | Watchdog circuit for monitoring programs and detecting infinite loops using a changing multibit word for timer reset | |
| JPS6220448A (ja) | ビツトサンプル方式 | |
| US5088035A (en) | System for accelerating execution of program instructions by a microprocessor | |
| US5293572A (en) | Testing system of computer by generation of an asynchronous pseudo-fault | |
| JP3211971B2 (ja) | データ入力および入出力装置 | |
| JPH0683488A (ja) | リセット制御回路 | |
| KR890007212Y1 (ko) | 동기화된 위치 데이터 리이드 회로 | |
| JPH0732415B2 (ja) | データ伝送方法及び装置 | |
| JPS61201362A (ja) | ウエイトサイクル插入回路 | |
| SU1005062A1 (ru) | Устройство дл исправлени последствий сбоев | |
| SU1553984A1 (ru) | Микропрограммный процессор | |
| JPH04106637A (ja) | ストール検出回路 | |
| JPH04260910A (ja) | 中央処理装置のクロック停止回路 | |
| JPS6029975A (ja) | 磁気ディスク制御装置 | |
| JPS6247750A (ja) | 記憶装置 | |
| JPH0234071B2 (cg-RX-API-DMAC7.html) | ||
| JPS61109154A (ja) | 固定デ−タ・レジスタのエラ−検出方式 | |
| JPH04332071A (ja) | マルチファームウェアの立ち上げ同期方式 | |
| JPS6239782B2 (cg-RX-API-DMAC7.html) | ||
| JPS6125167B2 (cg-RX-API-DMAC7.html) | ||
| JPS62111329A (ja) | 制御回路の異常出力防止方法および回路 | |
| JPH01189749A (ja) | 割込み制御方法 | |
| JPH01286549A (ja) | 障害項目表示回路 | |
| JPH0363776B2 (cg-RX-API-DMAC7.html) | ||
| JPS6148057A (ja) | アドレス選択回路 |