JPS62196350U - - Google Patents
Info
- Publication number
- JPS62196350U JPS62196350U JP8569986U JP8569986U JPS62196350U JP S62196350 U JPS62196350 U JP S62196350U JP 8569986 U JP8569986 U JP 8569986U JP 8569986 U JP8569986 U JP 8569986U JP S62196350 U JPS62196350 U JP S62196350U
- Authority
- JP
- Japan
- Prior art keywords
- container
- buffer layer
- lid
- resin layer
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000005192 partition Methods 0.000 claims 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の一実施例を示す断面図、第２
図、第３図はそれぞれ本考案の異なる実施例を示
す断面図である。
１：基板、２：側壁、３：蓋体、４：トランジ
スタチツプ、５：端子導体、７：緩衝層、８：樹
脂層、９：放圧弁、１０：溝。
Fig. 1 is a sectional view showing one embodiment of the present invention;
3 are sectional views showing different embodiments of the present invention. 1: Substrate, 2: Side wall, 3: Lid, 4: Transistor chip, 5: Terminal conductor, 7: Buffer layer, 8: Resin layer, 9: Pressure relief valve, 10: Groove.
Claims (1)
なる容器の基板上に一つまたは複数の半導体素子
が固定され、容器内に素子を被覆するゲル状緩衝
層および硬化樹脂層が充填され、素子に接続され
る端子導体が緩衝層および樹脂層を通つて蓋体か
ら引き出されるものにおいて、容器を貫通し緩衝
層に達する、容器より機械的に弱い隔壁を備えた
放圧通路が設けられたことを特徴とする半導体装
置。 One or more semiconductor elements are fixed on the substrate of a container consisting of a thermally conductive substrate, an insulating side wall, and a lid, and the container is filled with a gel-like buffer layer and a cured resin layer to cover the elements. , in which the terminal conductor connected to the element is drawn out from the lid through the buffer layer and the resin layer, a pressure relief passage is provided that penetrates the container and reaches the buffer layer and is equipped with a partition wall that is mechanically weaker than the container. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8569986U JPH0436119Y2 (en) | 1986-06-05 | 1986-06-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8569986U JPH0436119Y2 (en) | 1986-06-05 | 1986-06-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62196350U true JPS62196350U (en) | 1987-12-14 |
| JPH0436119Y2 JPH0436119Y2 (en) | 1992-08-26 |
Family
ID=30941338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8569986U Expired JPH0436119Y2 (en) | 1986-06-05 | 1986-06-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0436119Y2 (en) |
-
1986
- 1986-06-05 JP JP8569986U patent/JPH0436119Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0436119Y2 (en) | 1992-08-26 |
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