JPS62188258A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the semiconductor integrated circuit having a high resistance value and a small area resistor by a method wherein a plurality of impurity diffusion regions are connected by performing a transverse diffusion, and the connected part is used as a resistor. CONSTITUTION:After a silicon oxide film 2has been formed on the semiconductor substrate consisting of an N-type epitaxial layer 1, apertures 3A and 3B are formed, and the distance l between the aperture parts 3A and 3B is set less than twice the transverse distance of diffusion of impurities introduced into an N-type epitaxial layer 1 in the process to be followed. Then, using the silicon oxide film as a mask, boron is introduced through the aperture parts 3A and 3B, a P-type region 4 is formed on the surface of an N-type epitaxial layer, and then the boron is diffused to the desired depth on the P-tye region by performing a heat treatment. Two P-type regions 4 are connected and a P-type diffusion region 4A is formed, and the connected part is turned to a high resistance region 5. Subsequently, the silicon oxide film 2 is removed, and after a silicon oxide film 2A has been provided again, an aperture part is provided on the prescribed part, and after an Al film has been coated on the whole surface, an Al wiring 6 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing a semiconductor integrated circuit having a resistive element.

[Conventional technology]

Conventionally, pinch resistors, epitaxial resistors, and the like have been used as resistors that require a high resistance value but do not have very high insulation accuracy, such as load resistors formed in semiconductor integrated circuits.

The pinch resistance is as shown in FIG.
An N+ type semiconductor region 12 was formed on the surface of the P-type resistance region 11 formed above, and a resistor having a high resistance value was formed by eliminating the low resistance region near the surface of the resistance region 11. . In FIG. 6, 13 is a silicon oxide film, and 6 is A! ! It's the wiring.

In addition, epitaxial resistors originally use an epitaxial layer that exhibits a high resistance value as a resistor, and by separating the epitaxial layer used as a resistor and forming contact I and high-concentration semiconductor regions for formation at both ends. It was manufactured.

[Problem that the invention seeks to solve]

However, the conventional method of forming a resistor in a semiconductor integrated circuit described above has a problem in that it requires a large area because each resistor must be individually insulated. Furthermore, the pinch resistor has the problem that the potential difference generated across the resistor cannot be set higher than the withstand voltage between the resistor region 11 and the N+ type semiconductor region 12 formed on the surface of the resistor region 11.

An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit having a resistor having a high resistance value and a small area.

[Means for solving problems]

The method for manufacturing a semiconductor integrated circuit of the present invention includes forming an insulating film on a semiconductor substrate of a -conductivity type, providing a plurality of openings in the insulating film, and introducing impurities of the opposite conductivity type through the openings. A method of manufacturing a semiconductor integrated circuit in which an impurity diffusion region is formed on a semiconductor substrate, wherein the distance between the openings provided in the insulating film is twice the lateral diffusion distance of the impurity introduced into the semiconductor substrate. It is set to less than twice that.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1 (a), silicon oxide 1IGt2 is formed on a semiconductor substrate consisting of an N-type epitaxial layer 1 with a specific resistance of 1 to 3 Ω, and then two openings 3A are formed by photolithography. , 3B are formed.The distance l between these two openings 3A and 3B is equal to 2 of the lateral diffusion distance of impurities introduced into the N-type epitaxial layer 1 in a later process.
Set within twice.

Next, as shown in FIG. 1(b), using the silicon oxide film 2 as a mask, boron is introduced through the openings 3A and 3B by a thermal diffusion method or the like, and the P wall region 4 is introduced into the N type epitaxial surface. form.

Next, as shown in FIG. 1(c), heat treatment is performed to diffuse the P wall region 4 to a desired depth. Through this heat treatment, the two P wall regions 4 are connected to form one P type diffusion region 4A, and in particular, the connection portion by diffusion becomes a high resistance region 5. Subsequently, silicon oxide film 2 is removed.

Next, as shown in FIG. 1(d), a silicon oxide film 2A is again provided on the entire surface, and then openings are provided in predetermined portions. Next, after depositing an Af film on the entire surface, patterning is performed, and AI
Wiring 6 is formed.

The P-type diffusion region 4A formed in this manner has a high resistance region 5 in the center and can therefore be used as a resistor. The resistance value is the opening part 3A shown in FIG.
, 3B can be adjusted by the distance l between them. That is, the closer l is to a value twice the lateral diffusion distance of boron introduced into the N-type epitaxial layer 1, the greater the resistance value can be obtained. In addition, the resistor formed in this way can be made smaller than the resistor formed in conventional semiconductor integrated circuits, and since there is no need to separate it into I'liI resistors, it is possible to improve the degree of integration. can.

FIG. 2 (a>, (+)) is a cross-sectional view of the semiconductor chip shown in step Mf for explaining the second embodiment of the present invention, in which two resistors connected in series are formed. It shows the case.

First, as shown in FIG. 2(a), a silicon oxide film 2 is provided on an N-type epitaxial layer 1, and then three openings 3A, 3B, and 3C are formed by photolithography.

At this time, the distance between the openings is l.

2' is within twice the lateral diffusion distance of boron, which is an impurity introduced into the N-type epitaxial layer 1 in the later process, as in the case of the first embodiment shown in FIG. 1(a). Set to . Subsequently, using the silicon oxide film 2 as a mask, boron is introduced to form the P wall region 4.

Next, as shown in FIG. 2(b), heat treatment is performed to diffuse and connect the three P wall regions 4 to a desired depth, forming a P type diffusion region 4A having high resistance regions 5, 5A. do. Subsequently, after removing the silicon oxide film 2, a silicon oxide film 2A is again formed on the entire surface. Next, this silicon oxide film 2A
After forming an opening in a predetermined portion of the substrate, an Al film is deposited on the entire surface and patterned to form the /l' wiring 6.

The resistor formed in this way is two resistors RA and RB connected in series, as shown in the equivalent circuit diagram in Figure 3, and the resistance value is also relatively wide. I can do it.

FIGS. 4(a) and 4(b) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a third embodiment of the present invention, in which a current limiting resistor is formed in the base region of a bipolar transistor. It shows.

First, as shown in FIG. 4(a), a P-type silicon substrate 2
After providing an N+ type buried region 21 on the substrate 0, an N type epitaxial layer 1 is grown on the entire surface, and a silicon oxide film 2 is formed on the surface thereof. Subsequently, openings 3A and 3D are provided in predetermined portions of this silicon oxide film 2, and boron is introduced to form a P wall region 4. At this time, the distance l between the openings 3A and 3D is 2 of the lateral diffusion distance of the P wall region 4 due to heat treatment.
Set it within double.

Next, as shown in FIG. 4(b), heat treatment is performed to diffuse and connect the two P wall regions to a predetermined depth, thereby forming a base region 22 which is a P type diffusion region. At this time, a high resistance region 5 serving as a resistance is formed at the connection portion by diffusion. Thereafter, an emitter region 23 and a collector contact region 24 are formed by introducing an N-type impurity such as phosphorus using a conventional technique. Next, a silicon oxide film is formed on the entire surface, and after openings are formed on each region, A! is deposited and patterned to form an emitter electrode 6A, a base electrode 6B connected to the base region 22 via a resistor, and a collector electrode 6C.

The bipolar transistor thus formed has a current limiting resistor in the base region 22, but since this resistor can be formed small, the area of the bipolar transistor does not particularly increase.

An equivalent circuit diagram of this bipolar transistor is shown in FIG.

〔Effect of the invention〕

As described in detail above, the present invention connects a plurality of impurity diffusion regions by lateral diffusion and uses this connection as a resistor, thereby achieving a semiconductor integrated circuit having a high resistance value and a small area resistance. There is an effect that the circuit can obtain.

[Brief explanation of drawings]

FIGS. 1(a) to 1(d) are cross-sections of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention. 2(a) and 2(b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the second embodiment of the present invention, and FIG. 3 is shown in FIG. 2(b). Equivalent circuit diagram of a resistor; FIGS. 4(a) and 4(b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the third embodiment of the present invention; FIG. 5 is a diagram of FIG. 4(b). The equivalent circuit diagram of the bipolar transistor shown in
FIG. 6 is a cross-sectional view of an example of a resistor of a conventional semiconductor integrated circuit. 1... N-type epitaxial layer, 2, 2A... silicon oxide film, 3A, 3B, 3C, 3D... opening portion, 4.
... P wall region, 4A ... P type diffusion region, 5 ... high resistance region, 6 ... Ae wiring, 6A ... emitter electrode,
6B...Base electrode, 6C...Collector electrode, 10
. . . N-type semiconductor substrate, 11 . . . P-type resistance region, 12
... N+ type semiconductor region, 13... silicon oxide film,
20...P type silicon substrate, 21...N+ type buried region, 22...base region, 23...emitter region, 24...collector contact region. ) 1゜1st interval $ 3 Bacterial measures Otsu Figure

Claims (1)

[Claims] A semiconductor in which an insulating film is formed on a semiconductor substrate of one conductivity type, a plurality of openings are provided in the insulating film, and impurities of the opposite conductivity type are introduced through the openings to form an impurity diffusion region on the semiconductor substrate. A semiconductor manufacturing method for an integrated circuit, characterized in that the distance between the openings provided in the insulating film is set to be equal to or less than twice the lateral diffusion distance of impurities introduced into the semiconductor substrate. A method of manufacturing integrated circuits.