JPS60152051A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a capacitor having high capacitance by changing the surface of a semiconductor substrate or an epitaxial growth layer into irregularities, widening the surface area and annexing a dielectric film and an electrode on the surface. CONSTITUTION:Openings are bored to a diffusion preventive film 2 formed on a semiconductor substrate 1 in a striped or reticulate manner, an impurity is diffused and introduced through the openings, the film 2 is removed and striped or reticulate recesses are formed to the surface of the substrate 1. A dielectric film 2' is shaped to the surface of the substrate 1, and an electrode 4 is formed on the film 2'. Accordingly, a capacitor having capacitance large in comparison with the ratio of an occupying area on the substrate can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of industrial lambda
The present invention relates to a semiconductor device including a capacitor having a ter-3 semiconductor, or ) structure.

Conventional configuration and considerations Semiconductor integrated circuits often include capacitors.

When forming a capacitor, the simplest method is PN
This method uses junction capacitance, but its use is limited because the capacitance is small and it is voltage dependent.

Another method is to use an MIS structure.

This method will be explained with reference to FIG.

p-type silicon substrate or p-type silicon substrate grown on a silicon substrate
The surface of the mold epitaxial layer 1 is oxidized to form a silicon dioxide layer 2 (Si02). Using well-known photolithography and etching methods, Si02
Open the layer. Here, phosphorus is deposited as an N-type impurity,
FIG. 3a shows the result of diffusion to form an N-type region 3.

This process is used for NPN (NPN) type integrated circuits.
This is done at the same time as forming the emitter region of the transistor.

Subsequently, a portion of the capacitor is opened by similar photolithography and etching, as shown in FIG. Then, as shown in FIG. 3C, a thin silicon dioxide film 2' is formed as a dielectric film over the opening by thermal oxidation or CVD. In order to obtain ohmic contact with the silicon, an opening is made in the oxide film, and a contact electrode to the gap 1'' and the other electrode portion 4 of the capacitor are formed of a well-known aluminum evaporated film.

The capacitance of the capacitor obtained by the method shown in Figure 1 is
Small, typically formed in integrated circuits, are 100p
Up to F. What overcomes this limit is the thickness of the dielectric film and the capacitor surface U.
If we reduce the thickness of the dielectric material to avoid increasing the total dielectric strength, the dielectric strength will drop. An increase in the area of the cut capacitor increases production costs and must be avoided. OBJECTS OF THE INVENTION The present invention provides a manufacturing method for forming a capacitor with a higher capacitance than ever before in a semiconductor integrated circuit.

Structure of the Invention To summarize, the present invention provides openings in a diffusion prevention film formed on a semiconductor substrate or an epitaxial growth layer in the form of stripes or a mesh, and then diffusing and introducing impurities through the openings. forming the striped or striped depressions on the surface of the semiconductor substrate or the epitaxial growth layer by removing the film, forming a dielectric film on the surface of the semiconductor substrate or the epitaxial growth layer, and then forming the dielectric film on the surface of the semiconductor substrate or the epitaxial growth layer. This is a manufacturing method for semiconductor devices that includes a step of forming electrodes on the semiconductor substrate or epitaxial growth surface, thereby enlarging the surface area of the semiconductor substrate or epitaxial growth surface, and then attaching a dielectric film and electrodes thereon. Then, MIS
By forming a capacitor with a type structure, it is possible to realize a capacitor with a large capacity relative to the proportion of the area occupied on the substrate.

DESCRIPTION OF EMBODIMENTS FIG. 2 is a flowchart of manufacturing a bipolar integrated circuit according to a manufacturing method according to an embodiment of the present invention.

A p-type silicon substrate 1 is thermally oxidized to form a silicon dioxide film 2 on its surface, and then openings are formed at desired positions using well-known photolithography and etching methods, as shown in FIG.
It is. Of Figure 2 a.

The left side is a region where a bipolar NPN transistor is to be formed, and the right side is a region where a MIS structure capacitor is to be formed. At this time, a thin striped or net-like pattern is formed in the right inll region. and,
A buried layer 5 is formed by vapor deposition and diffusion of As-1 as an N-type impurity, as shown in FIG. At this time, the buried layer 6 on the capacitor side is connected integrally. In order to form an MIS type capacitor, it is essentially unnecessary to form a buried layer in that region. However, since the growth rate of the oxide film formed during the diffusion process 1 is different between the opening and the unopened area, unevenness is formed on the surface of the noricon. Therefore, in the region where the condenser on the right (ill) is formed, the surface area of silicon is large due to the unevenness.Therefore, as shown in FIG. , the unevenness is reproduced up to the first point.In addition, in Fig. 2C,
The N-type epitaxial layer 6 can be electrically isolated by a P-type isolation diffusion layer 7.

Next, as shown in FIG. 2d, when forming the collector low resistance layer 8, a mesh pattern is formed in the capacitor region in the same manner as in FIG. Further increase the surface area of the silicon.

A p-type base region 9 is formed, and N7. A qq emitter region 3 is formed. This is the same as the conventional example shown in FIG. The area has many irregularities on its surface, increasing the actual surface area.

FIG. 3 is an enlarged sectional view of the capacitor region. After that, the capacitor region is opened in the same manner as in the conventional method, and a silicon dioxide film 2' as a dielectric film is formed by thermal oxidation or CVD. After forming an opening and an electrode to obtain ohmic contact with silicon, an aluminum vapor-deposited film electrode 4 was formed.

By going through the above steps, the capacitor's capacity can be increased without increasing the surface roughness of the semiconductor substrate or adding any process by increasing the fruitful surface of the capacitor and rJli: This made it possible to increase the number of people. At the current stage, it is possible for the community to increase capacity by 10 to 40% compared to conventional products.

In the example, the process of forming irregularities on the silicon surface was a process of forming an N-type impurity layer in the capacitor region, but what is the impurity diffusion layer formed in the capacitor region? It is also important to form unevenness during diffusion and oxidation of a dielectric type impurity layer.

Effects of the Invention According to the present invention, the capacity of an MIS type capacitor included in a semiconductor integrated circuit can be increased without changing any conventional process. This is due to the fact that in the pre-process, which has not been used in the past in the capacitor field, the difference in the growth rate of the alignment film is used to create irregularities on the silicon surface and increase the substantial surface area. be.

[Brief explanation of drawings]

Figure 1 a y c Q, MIS configuration f1 according to the conventional example (
FIG. 2 a = d is a process flow chart showing the manufacturing method of the NPN bipolar transistor and MIs according to the present invention.
FIG. 3 is a sectional view showing a MIS capacitor manufactured by the manufacturing method of the present invention. 1... P-type semiconductor substrate casing or Ebitaki soyral layer, 2... Noricon dioxide layer, 3 N''-type emitter and capacitor partial diffusion layer, 4... Aluminum vapor deposition Membrane'+ji: pole, 5...N buried diffusion layer, 6...N-type evixial layer, T...
...P Molecule'71N diffusion layer, 8...N Collector low resistance layer, 9...NPN) Base diffusion layer of transistor. Name of agent: Patent attorney Toshio Nakao and one other name
1 Figure 2

Claims (1)

[Claims] A diffusion prevention film formed on the semiconductor substrate or epitaxial growth layer is opened in a striped or mesh pattern, and impurities are diffused and introduced through the openings, and then the diffusion prevention film is removed and the surface of the semiconductor substrate or epitaxial growth layer is removed. manufacturing a semiconductor device, comprising the steps of forming the striped or mesh-like recesses, forming a dielectric film on the surface of the semiconductor substrate or epitaxial growth layer, and then forming an electrode on the dielectric film. Method.