JPS6154664A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration, and to lower parasitic capacitance between a collector and a base and base resistance by forming a device in vertical type structure, shaping a base leading-out section to the side wall of a base region and constituting the base leading-out section by a metal. CONSTITUTION:An n<+> type GaAs layer 2 and an n<-> type GaAs layer 3 (a collector) are formed onto a semi-insulating GaAs substrate 1. An SiO2 layer 6 a refractory metal layer 7 and an SiO2 layer 8 are shaped in succession. The layers 8-6 are removed from a section corresponding to an emitter-base forming region 9 and a section on a collector-electrode leading-out region 3'. A p type GaAs layer 11 (a base) is formed in the region 9 so as to be in contact with the layer 7, and an n type AlGaAs layer 12 (an emitter) and an n<+> type GaAs layer 13 are shaped onto the layer 11. The layer 8 is removed from a base-electrode forming region, and base electrode 14, an emitter electrode 15 and a collector electrode 16 are each formed into said base-electrode forming region, onto the layer 13 and into the region 3'.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device. In particular, in a heterojunction bipolar transistor in which an emitter and a base collector are stacked to form a vertical structure, the base extension portion is formed on the side wall of the base region.

The present invention relates to improvements that increase the degree of integration, reduce collector-base parasitic capacitance, and further reduce base resistance.

(2) Background of the Technology As a category of bipolar transistors, there is a semiconductor device called a heterojunction transistor made of a compound semiconductor. This is because the bandgap of the semiconductor that makes up the emitter is larger than the bandgap of the semiconductor that makes up the base.In this case, the barrier to holes between the emitter and base becomes high, so holes flow from the base to the emitter. This has the advantage that the resistance of the base can be lowered without adversely affecting the current amplification factor, and the possibility of punch-through phenomenon occurring in shallow junctions is reduced, making it easier to use as a high-speed device. A method has also been proposed in which the bandgap of the semiconductor constituting the base is increased in a gradient manner from a region in contact with the collector to a region in contact with the emitter, thereby producing a similar effect.

(3) Prior art and problems Heterojunction bipolar transistors in the prior art generally have a planar structure, and the base extension is made of the same material as the base region, so the base resistance is not necessarily low enough to be satisfactory. However, there is still room for improvement in that it is difficult to resist, and there has been a desire to develop a heterojunction bipolar transistor with low base resistance.

(4) Purpose of the Invention The purpose of the present invention is to meet this demand.The present invention has a vertical structure in which the base extension part is formed on the side wall of the base region, and has a high degree of integration, thereby reducing the parasitic capacitance between the collector and the base. The object of the present invention is to provide a heterojunction bipolar transistor having a low base resistance and a base lead portion made of metal.

(5) Structure of the Invention The structure of the present invention is that a first insulating layer is formed on a first semiconductor layer (collector) of one conductivity type, except for a part of the region, and on the first insulating layer. A refractory metal layer is formed on the refractory metal layer, and a second insulating layer is formed on the one region in contact with the refractory metal layer and has a conductivity type opposite to the l conductivity type. A second semiconductor layer (base) is formed on the second semiconductor layer (base) in contact with the second insulating layer and has a larger band gap than the first semiconductor and is the same as the l conductivity type. A third semiconductor layer (emitter) of a conductivity type is formed, an emitter electrode is formed connected to the third semiconductor layer (emitter), and a base electrode is formed connected to the refractory metal layer, A semiconductor device includes a collector electrode connected to the first semiconductor layer (collector).

(6) Embodiments of the Invention The manufacturing process of a heterojunction bipolar transistor according to an embodiment of the present invention will be further described below with reference to the drawings.

See Figure 1 Molecular beam epitaxy method or metal organic CVD
10 on a semi-insulating gallium arsenide substrate l using a method etc.
Contains n-type impurities at around 20c■-3 and has a thickness of 5,000mm
A gallium arsenide layer 2 (collector electrode contact layer) with a thickness of approximately 1,018 cm + -3 and a gallium arsenide layer 3 (collector φ first semiconductor layer) with a thickness of approximately 5,000 cm containing n-type impurities. Continue to form.

Then, chromium, H+ ions, etc. are selectively introduced into the element isolation region 4 and the collector-collector electrode isolation region 5 to convert these regions 4.5 into insulating layers as shown in the figure. This step can be easily performed using an ion implantation method using a mask.

Refer to FIG. 2 Next, an n-type impurity is introduced into the collector electrode lead-out region 3' to form a highly doped n-type layer.

Using CVD method etc., a silicon dioxide layer 6 (first insulator layer) of about 1,000 layers thick is formed, and a frac metal such as tungsten, molybdenum, titanium, etc. is evaporated and the thickness is increased. A frac-remetal layer 7 with a thickness of 500 to 1,000 thick is formed, and a silicon dioxide layer 8 with a thickness of about 2,000 thick is further formed using a CVD method or the like.

Refer to FIG. 3. The three layers of silicon dioxide layer 8, refractory metal layer 7, and silicon dioxide layer 6 are divided into a portion corresponding to the emitter/base formation region 9 on the gallium arsenide layer 3 and a portion 3° above the collector electrode lead-out region. and remove from. This step can be easily performed by combining chemical etching and active ion etching.

See Figure 4 Molecular beam epitaxy method or metal organic CVD
Using an emitter-base type method etc., a gallium arsenide layer 11 containing p-type impurities (base-second semiconductor 1017 to 1018 are formed on the silicon dioxide layer 8 so as to be in contact with the silicon dioxide layer 8.
When forming the base region for forming the aluminum gallium arsenide layer 12 (emitter/third semiconductor layer) containing n-type impurities in C11-3, aluminum is mixed as it progresses toward the emitter side to widen the band gap. It may also be a process of expanding. In the outermost layer, a gallium arsenide layer 13 containing n-type impurities at a high concentration of about 10@20 cm@-3 is formed to a thickness of about several hundred as an emitter electrode contact layer.

Referring to FIG. 5, the silicon dioxide layer 8 is removed from the base electrode formation region, and a gold/germanium layer is selectively formed in this region, the emitter electrode contact layer 13, and the collector electrode extraction region 3'. Thus, a base electrode 14, an emitter electrode 15, and a collector electrode 16 are formed, respectively.

In the semiconductor device manufactured using the above process, (a) the emitter is composed of a semiconductor (aluminum gallium arsenide) with a larger band gap than the semiconductor composing the base (gallium arsenide), which adversely affects the current amplification factor. The base impurity concentration is 1019C without any adverse effects.
The base resistance has been lowered by increasing the resistance to about I+-3, (b) the resistance of the base lead-out part has been sufficiently reduced since the base lead-out part is constructed with a frac-remetal layer, and (c) the emitter resistance has been lowered. Since the base and collector are stacked to form a vertical structure, it is easy to improve the degree of integration, and the parasitic capacitance between the collector and base is also reduced, which significantly improves the switching speed. This is extremely advantageous as a high-speed device.

In the above embodiments, a combination of gallium arsenide and aluminum gallium arsenide is used, but the requirements for constructing a heterojunction bipolar transistor are that a good petrojunction can be formed, and that ,
Any combination of semiconductors with different bandgaps can be used.

Further, it goes without saying that the manufacturing process shown above is only one example.

(7) As described in detail, the present invention has a vertical structure, the base extension part is formed on the side wall of the base region, the degree of integration is high, and the parasitic capacitance between the collector and the base is low. The base extension portion is made of metal, so that a heterojunction bipolar transistor with low base resistance can be provided.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views of a substrate after completion of the main manufacturing steps of a heterojunction bipolar transistor according to an embodiment of the present invention. 1: Semi-insulating gallium arsenide substrate, 2: N-type gallium arsenide layer (collector electrode contact layer), 3:
n-type gallium arsenide layer (collector/first semiconductor layer),
3°...ΦCollector electrode extraction region, 4...Element isolation region, 51.Collector collector electrode isolation region,
6... Silicon dioxide layer 6 (first insulator layer) 7...
・Refractory metal layer, 8 layers ・・Silicon dioxide layer (second insulator layer), 9 ・ ・ ・Emitter・
Base formation region, lO...Φ collector electrode formation region,
11...p-type gallium arsenide layer (base #second semiconductor layer), 12...@n-type aluminum gallium arsenide layer (emitter/third semiconductor layer), 13Φ/fist n-type gallium arsenide layer (emitter electrode contact layer), 14-
- Base electrode, 15... Emitter electrode, 16.
・-Collect Q) Taste

Claims (1)

[Claims] A first insulating layer is formed on a first conductivity type first semiconductor layer (collector) except for a part of the region, a refractory metal layer is formed on the first insulating layer, and a refractory metal layer is formed on the first insulating layer. a second insulating layer is formed on the metal layer, a second semiconductor layer (base) of a conductivity type opposite to the first conductivity type is formed on the one region in contact with the refractory metal layer; a third semiconductor layer (emitter) on the second semiconductor layer (base), in contact with the second insulating layer, and having a larger band gap than the first semiconductor and the same conductivity type as the first conductivity type;
is formed, an emitter electrode is formed connected to the third semiconductor layer (emitter), a base electrode is formed connected to the refractory metal layer, and the first semiconductor layer (
A semiconductor device in which a collector electrode is formed by connecting the collector to the collector.