JPS61218168A - Manufacture of semiconductor device with graft base - Google Patents

Abstract

PURPOSE:To improve the microminiaturization and a withstand voltage between an emitter and a base by forming an emitter and a graft base in a self-aligning manner. CONSTITUTION:After a low density P-type layer 12 to become an intrinsic base is formed on an Si semiconductor substrate 11, a mask material is formed thereon, a window hole 16 is opened, and an emitter is diffused through the hole 16 to form a high density n-type high density layer 17. Then, a polysilicon layer 18a is formed in the hole 16 with the step of the mask material. Then, with the layer 18a as a mask high density p-type impurity is implanted to the surface of the substrate to form a graft base layer 20. Thus, since the emitter region 17 and the graft base region 20 are formed in a self-aligning manner, a microminiaturization of the device can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device having a graft base using self-alignment (self-alignment technology), and mainly relates to a technique for manufacturing a graft base IIL.

[Background technology]

The performance of high-speed Piborad 2 transistors is determined by the cut-off frequency (f
t) and the base resistance (rbb'). In order to obtain a high ft, it is effective to form a shallow junction and to reduce the parasitic capacitance by making the transistor gold smaller, but this tends to increase rbb', and it is difficult to simply make the standard transistor smaller. Doing so alone will not provide sufficient performance. Therefore, a graft base type transistor has been proposed in which the base and emitter are formed in a self-aligned manner using polycrystalline silicon T-, and the base width is narrow and the temporary concentration intrinsic base is deep and the graft base is deep and highly concentrated. Various manufacturing processes have been reported.

■Published by Science Form Company on November 18, 1982.
VLSI Device Handbook JP68-7 For example, according to the graft base formation method conventionally known as the selective oxidation method, as shown in FIGS. After forming a shallow low concentration P'''' type layer for the intrinsic pace, (2
) By applying mask pressure to the silicon nitride (S bN+ ) film 4 and diffusing B (boron)'t-, a deep 1!1 degree P-type layer 5 gold is formed to form a graft base (Fig. 14), (31 Due to oxidation, the surface portion of the Si-based substrate where 81, N, and film 4 are not formed Jlt/Jk film 6
(Fig. 15), (4) Remove the SisNia gold and use the above base oxide film 6 as a mask to diffuse the emitter and form n+
A mold layer 7 is formed (FIG. 16). (5) Poly 51t is then deposited on the entire surface and patterned using photoresist to obtain a poly Sl emitter electrode 8. (Figure 17). The reason why poly-Si is used for the electrode is that if the AJ electrode is directly connected to the 81 substrate, there is a risk that A will diffuse into 91 and destroy the shallow emitter junction, and poly-Sl is used to prevent this.

According to this method, since the poly S1 electrode does not depend on the cell 7 alignment, a large area is taken up by patterning, and the St
There is a problem that the coating surface graft base P type layer and the emitter NFI layer become close to each other, resulting in a decrease in emitter-base breakdown voltage.

Another conventionally known method for forming a graft base is the use of a polySt stack. As shown in FIGS. 18 to 20, this method is as follows: (1) After forming an intrinsic base P-type layer 2 on the surface of a Si substrate 1, a shallow emitter is diffused through the entire window hole of an oxide film 3. n+ layer 7 is formed, (18th
Figure), (2) Poly S1 ohmically connected to n+ type layer 7
Forming the emitter electrode 8 (Fig. 19), (3) PolyS
A digraft base P type layer 5t is formed by introducing B (boron) into the t-81 electrode 8t mask (
Figure 20).

Even in this method, since the poly S1 electrode does not depend on cell 7 alignment, mask alignment margin is required to avoid reducing the breakdown voltage between the graft base and emitter.
This poses a problem in that the emitter electrode overlaps the intrinsic base P42, resulting in increased capacitance.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned problems. Therefore, one object of the present invention is to obtain a high-performance semiconductor device formed by an emitter, a graft base, and a gold cell 7 aligned.

Another object of the present invention is to provide a semiconductor device such as an IIL with high breakdown voltage and no overlap between the graft base and the emitter.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, P which becomes an intrinsic paste on the surface of the S1 semiconductor substrate
- After the entire mold layer is formed, a mask material is provided on top of the mask material, a window hole is made, and the emitter is diffused through the entire window hole to form an n-type layer, and the entire step of the mask material is filled into the window hole. nipolyS
Form an i-layer and use this poly 81 m? The base for the graft base is diffused into the mask, and in this way, the emitter and the graft base are formed by self-alignment, making it possible to achieve a nine-dimensional miniaturization, which not only improves performance but also increases the emitter base breakdown voltage. can also be improved to achieve the above objective.

[Example 1] Figures 1 to 6 show an example of the present invention, in which a high-speed bipolar npn having a graft base
FIG. 3 is a cross-sectional view of a main part of a transistor manufacturing process.

Each step will be explained in detail below.

(17 As shown in Figure 1, an n-type St semiconductor device (usually an n"" type S
Prepare mold layer 1 layer 1, and apply a low concentration of B (boron) on its surface.
P is doped by t-ion implantation and becomes an intrinsic base.
- forming a mold layer 12; A thin nitride film (5isN4) 13 of approximately 100 OA is deposited on the surface of the P'' layer 120 in a gas phase at low temperature (470°C) at normal pressure or high temperature (700°C) at low pressure. Membrane (below) (LD membrane 1
4) to a thickness of about 15,000 A, and using the photoresist 15 as a mask, the HLD film and 5laN+ ['
A window hole 16 is made in the part that will become the emitter by etching.

(2) A high concentration of As (arsenic) t- ions are implanted and diffused into the surface of the P''''''12 through the entire window hole to form a shallow n+ diffusion layer 17 that will serve as an emitter. (Fig. 2) (3) Deposit 51t on the entire surface from the gas phase, and add a poly-Si film 18t-2000 to fill the window hole 16tl.
Formed to a thickness of ~3000A. Next, a resist 19'fc is applied thereon and etched, so that only the resist 19a in the hole 16 is left due to the step of the IJSi film 18 at the window hole 16 portion. By etching the poly 5i18t with this resist 19 left, the HL
The Si 18 on the D film 1 film 4 is etched to form the window hole 16.
Poly 5ij118& remains only in the cell 7 alignment (FIG. 3).

If the HLD film is thick enough to cover one film tube, as shown in Fig. 6, it should be formed sufficiently thick to fill the window hole 16t, and etched on the entire surface of the 9-poly 5i18t layer, so that the poly-polymer is only formed in the window hole. selectively remains as 81 conversion 18a, n+
The IJSi film 18 can be formed on the mold layer 17 in a self-aligned manner.

(4) Remove the HLD film by etching each film with an HF-based etchant, and then remove Si, N, and film 13 by etching with CHF, gas, or the like.

(5) By forming a thermal oxide film 21 on the substrate surface and implanting and diffusing B (boron) ions into the substrate, poly-Si
Using the layer 18m as a mask, the graft base P layer 20f is formed in a self-aligned manner as shown in FIG.

In addition, although not shown, a contact hole is made in the graft base portion, a base electrode is provided by AI vapor deposition, and an electrode is drawn out from the collector portion, thereby completing a high-speed bipolar NPN transistor.

[Effects of the Invention] According to the present invention described in Example 1, the following effects can be obtained.

(The 13-poly-S content converter 18a can be formed in a self-aligned manner with respect to the emitter by using the step of the oxide film used to form the emitter n+ type layer.

(2) By performing graft base diffusion using the poly 81 film 18a'i mask, the graft base can be formed in a self-aligned manner with respect to the emitter, thus making it possible to miniaturize the emitter.

(3) For the same reason as in (2) above, the graft base and emitter do not overlap with each other, and a high-voltage bibor 2 transistor can be obtained.

(4) Since it has a stud emitter structure using poly S1, the contact area can be reduced and it can be used in the case of a shallow emitter junction.

(5) A high-speed, large-capacity Pipo 2 transistor can be manufactured than in the above (1) to (4).

[Embodiment 2] FIGS. 7 to 12 show another embodiment of the present invention, and are cross-sectional views of main parts of the manufacturing process of IIL having a graft base. FIG. 13 is a plan view of the completed IIL corresponding to FIG. 12. Each step will be explained in detail below.

(1) An epitaxial n″″ff1si layer 22 is formed on the surface of an St substrate (not shown) as an n+ type buried layer 33t-.
The n'''' layer 22 is separated into island regions by a thick isolation layer 23. (FIG. 7) The surface of this n-type layer 22 island region has a thin 810. The film 24 and Si and N used as masks when performing isolation oxidation.

A film 25 is formed. This S is N2H425
For example, S10. Membrane (HLD)
i) Partially formed with a thickness of 26t-0.3 μm.

B (boron) ions are implanted into this HLDM 26 as a mask, and P-ffi layers 27 and 28, which serve as an intrinsic base, are selectively formed on the n'''' layer 81 fitting surface where the HLD film is not formed.

(2) Deposit the second HLD film 29 on the entire surface, photo-etch the emitter (collector in IIL) using a photoresist 30, open a window 31, and inject As (arsenic) into the St layer through the 9 parts. By ion implantation, an emitter (collector) n+ type diffusion bird 32 is formed as shown in FIG.

Note that when the window hole 31 is photo-etched, the second HLD film 29 is over-etched by 0.5 to 1 μm compared to the expanded photoresist 30.

(3) Remove the resist 30t and deposit poly-Sl to fill the window hole 31. jsIM34 is formed. Furthermore, by applying a resist 35 on this and plasma etching), the above-mentioned PO! As shown in FIG. 9, the resist film 35 on the window hole secondarily made in the JSilk 34 is left as shown in FIG. 9, and the other resist is removed.

(4) Remaining resist belly 35T - poly-Si layer 3 on mask
By wet etching, only the holes IJSij [36 above the window holes are left and the others are removed, as shown in FIG. 10.

(5) Remove the second HLD film 29 by wet etching,
Next, after removing Sl, N, and 25 by dry etching,
B (boron) is ion-implanted as shown in FIG.

(6) Stretch and diffuse into the B t Si substrate and
As shown in FIG. 2, the graft base P-type layer 37t is formed sufficiently deep. At this time, a P layer 38 which will serve as an injector is also formed. Next, an injector electrode area indicator 39 and a graft base electrode number indicator 40
Perform contact photoetch.

FIG. 13 is a plan view corresponding to FIG. 12, and shows the contact portions of the injector electrodes Injs, the collector electrodes C, C, and the base electrode B.

After this, although not shown in the drawings, the entire surface is covered with an inorganic or organic insulating film, through-hole photoetching (contact photoetching) is performed on necessary parts, and then M vapor deposition, annealing, and patterning etching are performed.A! forming electrodes (wiring), II
Complete L.

〔Effect of the invention〕

According to the present invention described in Example 2, the same effects as in Example 1 described above can be obtained, and a high-speed, large-capacity IIL
It became possible to manufacture '.

Although the invention made by the present invention has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof. do not have.

[Application field]

The present invention is also effective when applied to ultrafine (for example, 2 μm) processes such as IIL (including the case where linear circuits coexist on one substrate), bipolar memory, and the like.

The present invention can be similarly applied to transistor memories having a graft base such as ECL in addition to IIL.

[Brief explanation of the drawing]

FIGS. 1 to 5 show an embodiment of the present invention, and are process cross-sectional views of a bipolar transistor process having a graft base. FIG. 6 is a process sectional view showing a modification of the embodiment process shown in FIG. 3. FIGS. 7 to 12 show another embodiment of the present invention, and are process sectional views of an IIL process having a graft base. FIG. 13 is a plan view corresponding to FIG. 12. FIGS. 14 to 17 are process cross-sectional views showing an example of a conventional graft-based process. FIGS. 18 to 20 are process cross-sectional views showing another example of the conventional graft-based process. 11... n-type Sl substrate, 12... intrinsic base P-
mold layer, 13...Si, N, film, 14...HLD film,
15... Photoresist, 16... Window hole, 17...
Emitter n+ type layer, 18...poly-Si II, 19.
... Photoresist, 20 ... Graft base Pa layer,
21...sio, membrane. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5/Z Figure 6 Figure 13 Figure 18 Figure 19 Figure 20 Figure Z/

Claims (1)

[Claims] 1. A low concentration impurity doped layer serving as an intrinsic base is formed on the surface of a semiconductor substrate, a mask material is formed on this layer, and the substrate is exposed through a window hole made in a part of the mask material. After forming a high concentration impurity diffusion layer to serve as an emitter on a part of the surface, and then forming a polycrystalline semiconductor film on the emitter using the step of the mask material, the polycrystalline semiconductor film is used as a mask to form a polycrystalline semiconductor film on the base. 1. A method for manufacturing a semiconductor device having a graft base, which comprises introducing impurities into the surface to form a highly concentrated impurity diffusion layer that will become a graft base in a self-aligned manner. 2. The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate is made of n-type silicon, the intrinsic base and the graft base are made of a p-type silicon layer, and the emitter is made of an n-type silicon layer. Manufacturing method. 3. The method for manufacturing a semiconductor device having a graft base according to claim 2, wherein the semiconductor device is a bipolar npn transistor. 4. The semiconductor device is a reverse npn transistor in IIL (injection integrated logic), and has a graft base according to claim 2, the collector (multi-collector) of which corresponds to the emitter. A method for manufacturing semiconductor devices.