JPH01187863A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01187863A JPH01187863A JP1063888A JP1063888A JPH01187863A JP H01187863 A JPH01187863 A JP H01187863A JP 1063888 A JP1063888 A JP 1063888A JP 1063888 A JP1063888 A JP 1063888A JP H01187863 A JPH01187863 A JP H01187863A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- silicon
- semiconductor layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 2
- 239000010409 thin film Substances 0.000 claims description 2
- 230000003321 amplification Effects 0.000 abstract description 10
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 125000005842 heteroatom Chemical group 0.000 abstract 3
- 239000010408 film Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- LELOWRISYMNNSU-UHFFFAOYSA-N hydrogen cyanide Chemical compound N#C LELOWRISYMNNSU-UHFFFAOYSA-N 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ヘテロ接合を有するシリコンコンバイポーラ
半導体装置に係り、特に電流増幅率および遮断周波数が
大きい半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a silicon combiner semiconductor device having a heterojunction, and particularly to a semiconductor device having a large current amplification factor and cutoff frequency.
従来、バイポーラトランジスタの性能、特に電流増幅率
や遮断周波数の向上は主として微細加工技術の改善で進
められて来たが、限界に近づきつつある。バイボーラン
トランジスタの遮断周波数は、エミッタ・ベース接合部
の時定数、ベース層の走行時間、コレクタ空乏層の走行
時間、ベース・コレクタ接合部の時定数などに依存する
が、微細化された最近のシリコンバイポーラトランジス
タでは、接合部の時定数（特にエミッタ・ベース接合部
）の影響が大きい。この時定数を低減するには、エミッ
タ部の禁制帯幅をベース部より広くして、エミッタ部へ
の注入電流を減少させることが効果的である。そこで、
ヘテロ接合構造を用いる方法が提案されている。Conventionally, improvements in the performance of bipolar transistors, particularly in current amplification factor and cutoff frequency, have been made primarily through improvements in microfabrication technology, but this is approaching its limits. The cutoff frequency of a biborane transistor depends on the time constant of the emitter-base junction, the transit time of the base layer, the transit time of the collector depletion layer, the time constant of the base-collector junction, etc. In silicon bipolar transistors, the time constant of the junction (especially the emitter-base junction) has a large effect. In order to reduce this time constant, it is effective to make the forbidden band width of the emitter part wider than that of the base part to reduce the current injected into the emitter part. Therefore,
A method using a heterojunction structure has been proposed.
ヘテロ接合構造を用いる方法として、シリコンよりも禁
制帯幅の広い炭化珪素（佐々木他、第１７回固体素子コ
ンファレンス予稿集、東京。As a method using a heterojunction structure, silicon carbide, which has a wider forbidden band width than silicon (Sasaki et al., Proceedings of the 17th Solid State Device Conference, Tokyo), is used.
１９８５、ｐ、３８５−３８８）や非晶質シリコン（た
とえばインターナショナル・ミーティング・デニカル・
ダイジェスト（Ｉｎｔｅｒｎａｔｉｏｒ＋ａｌＥｌｅｃ
ｔｒｏｎ Ｄｅｖｉｃｅｓ Ｍｅｅｔ：ｊｎｇ、 Ｔｅ
ｃｈｎｉｃａｌ Ｄｉｇｅｓｔ）第７４６頁、１．９８
４）を用いた方法が発゛表されている。これらのへテロ
接合素子では、電流増幅率が数十と小さい問題がある。1985, p. 385-388) and amorphous silicon (e.g. International Meeting Denical
Digest (International+alElec
tron Devices Meet: jng, Te
Chnical Digest) p. 746, 1.98
A method using method 4) has been developed. These heterojunction devices have a problem in that their current amplification factors are as small as several tens of tens of magnitude.
また、ベース部を高濃度にドープし禁制帯幅を縮小した
り、禁制帯幅の小さい５ｉＧｅ合金半導体をベース層に
用いる方法がある。Further, there is a method of doping the base portion with a high concentration to reduce the forbidden band width, or using a 5iGe alloy semiconductor having a small forbidden band width for the base layer.
上記従来技術においては、電流利得が数十であり、シリ
コンバイポーラトランジスタの１００以上に比べて小さ
いと言う問題がある。また、集積回路に適用した場合１
表面段差が大きく、応力の集中しやすい形状となる問題
もある。The above-mentioned conventional technology has a problem in that the current gain is several tens, which is smaller than the 100 or more of a silicon bipolar transistor. Also, when applied to integrated circuits, 1
There is also the problem that the surface level difference is large and the shape tends to concentrate stress.
本発明の目的は、前記従来技術の欠点がなく。The object of the present invention is to avoid the drawbacks of the prior art mentioned above.
電流増幅率および遮断周波数が大きく、さらに表面段差
が小さく結晶欠陥の発生しにくいバイポーラデバイスを
提供することにある。It is an object of the present invention to provide a bipolar device that has a large current amplification factor and cutoff frequency, has small surface steps, and is less likely to generate crystal defects.
上記第１の問題点は、禁制帯幅の小さいシリコン・ゲル
マニューム合金をベース層に用い、禁制帯幅の広いヒ化
ガリウム等の半導体をエミッタに用いることにより解決
される。また、上記第２の問題点は、素子の表面段差部
を２種類あるいはそれ以上の種類のＷｉ膜を用いて平坦
化することによって解決される。The first problem can be solved by using a silicon-germanium alloy with a small forbidden band width for the base layer and using a semiconductor such as gallium arsenide with a wide forbidden band width for the emitter. Further, the second problem can be solved by flattening the surface step portion of the element using two or more types of Wi films.
本発明によるヘテロ接合の特徴を第１図および第２図を
用いて説明する。The characteristics of the heterojunction according to the present invention will be explained using FIGS. 1 and 2.
第２図は、ｎ形Ｓｉ半尊体とｐ形単結晶Ｓ 、ｉ Ｇ
ｅとのへテロ接合のバンド構造図である。分子線エピタ
キシャル法で形成したＰ形Ｓｉｏ、５Ｇｅｏ、２半導体
の禁制帯幅は１．ＯｅＶで、ヘテロ接合の価電子帯のエ
ネルギー差（ΔＥｖ）はＯ，ｔ５ｅＶ である。Figure 2 shows an n-type Si semiconductor and a p-type single crystal S, iG.
It is a band structure diagram of a heterojunction with e. The forbidden band width of the P-type Sio, 5Geo, 2 semiconductor formed by molecular beam epitaxial method is 1. At OeV, the energy difference (ΔEv) of the valence band of the heterojunction is O,t5eV.
このため、正孔のエミツタ層への注入が阻止される。ま
た、第１図は、ｎ形Ｓ３半導体をコレクタに、ｐ形ｍ結
品５ｉＧｅをベースに、ｎ形ＧａＡｓをエミッタに用い
たヘテロ接合トランジスタのバンド構造図である。エミ
ツタ層に用いたＧ ａ Ａ ｓの禁制帯幅は１．４ｅＶ
とＳｉよりも大きく、ヘテロ接合の価電子帯のエネル
ギー差は０．３ｅＶ以上と非常に大きくなる。このため
、第１図の１．青酸にすると第２図の構成よりも更に電
流増幅率が向上し、高周波特性が良くなる。This prevents holes from being injected into the emitter layer. Further, FIG. 1 is a band structure diagram of a heterojunction transistor using an n-type S3 semiconductor as a collector, a p-type m-type 5iGe as a base, and an n-type GaAs as an emitter. The forbidden band width of Ga As used for the emitter layer is 1.4 eV
is larger than that of Si, and the energy difference between the valence bands of the heterojunction is as large as 0.3 eV or more. For this reason, 1. in Figure 1. When hydrocyanic acid is used, the current amplification factor is further improved than in the configuration shown in FIG. 2, and the high frequency characteristics are improved.
エミッタ用材料としてはＧａ Ａ ｓの他に、ＳｉＣや
微結晶Ｓｉ（μＣ−８ｉ）等のの材料を用いることもも
ちろん可能である。As the material for the emitter, other than GaAs, it is of course possible to use materials such as SiC and microcrystalline Si (μC-8i).
以下、本発明の詳細な説明する６
まず、ＮＰＮ型高周波トランジスタへの本発明の適用例
につき、第３図を用いて説明する。The present invention will be explained in detail below.6 First, an example of application of the present invention to an NPN type high frequency transistor will be explained with reference to FIG.
１．２．３はそれぞれエミッタ電極、ベース電極、コレ
クタ電極である。Ｐ中外部ベース層およびＮ＋コレクタ
層は公知のイオン打込み法あるいは熱拡散法で作製する
。、ｐ形ベース層５およびＮ十形エミツタ層４は通常の
エピタキシャル成長法で形成されたＮ−層の上に、分子
線エピタキシャル成長法を用いて成長し、ヘテロ接合を
形成する。1.2.3 are an emitter electrode, a base electrode, and a collector electrode, respectively. The P inner and outer base layers and the N+ collector layer are fabricated by a known ion implantation method or thermal diffusion method. , the p-type base layer 5 and the N-type emitter layer 4 are grown by molecular beam epitaxial growth on the N- layer formed by normal epitaxial growth to form a heterojunction.
まず、Ｂトープのｐ形Ｓｉｏ、ａＧｅｏ、ｘ半導体層を
形成し、その上にＳｉドープのＮ十形Ｇ ａ Ａ Ｓ半
導体層を形成した。ベース電極はエミツタ層４をエツチ
ングしてから、Ｐ十形を形成し、その上に形成した。得
られたヘテロ接合トランジスタの電流増幅率は約３００
と良好な値を示した。First, B-tope p-type Sio, aGeo, x semiconductor layers were formed, and a Si-doped N0-type GaAs semiconductor layer was formed thereon. The base electrode was formed by etching the emitter layer 4, forming a P-shape, and then forming the base electrode thereon. The current amplification factor of the obtained heterojunction transistor is approximately 300
showed a good value.
第４図は、集積回路用ＮＰＮ型トランジスタに本発明を
適用した実施例で、コレクタ電極をウェハ上面から取り
出している点が第３図と異なっている。FIG. 4 shows an embodiment in which the present invention is applied to an NPN transistor for an integrated circuit, and is different from FIG. 3 in that the collector electrode is taken out from the upper surface of the wafer.
また、第５図は本発明を側壁ベース電極（ＳｉＣＯ８）
型高性能バイポーラトランジスタに適用した実施例であ
る。ｐ形シリコン層板にＮ十形埋込層を設けに後、分子
線エピタキシャル成長法で、ＰをドープしたＮ−形シリ
コン層、ＢドープのＰ形Ｓｉｏ、ａＧｅｏ 、 ｘ層５
を形成した後、能動領域を残してエピタキシャル成長層
をエツチングし、５ｉ０２膜６を介して多結晶シリコン
膜７を埋込みＢを高濃度にドーピングした後、表面にパ
ッシベーション用（７）ＳｉＯｚ膜８を形成し、さらに
５ｉ３Ｎａ膜９ を全面に堆積した。ここで、表面に生
じた凹部を平坦化するためにＰＳＧ膜（リンガラス膜）
あるいはＢＰＳＧ膜（ボロン・リンガラス膜）あるいは
ノン・ドープの５ｉＯｚｌｌｊｆｉｌｏを堆積・エツチ
ングした。次に、エミッタの孔開けを行ない、再び分子
線エピタキシャル成長法で、ＳｉをドープしたＮ十形Ｇ
ａＡｓ層４を選択的に形成した。そして、コンタクトの
孔開は後、エミッタ電極１１ベース電極２．コレクタ電
極３を形成してトランジスタが完成した。作製した集積
回路用トランジスタの電流増幅率は約３００で、その遮
断周波数は約２５ Ｇ Ｈｚと高かった。また、ベース
取出し電極による表面段差を多層膜の埋込みによって平
坦化しているので、電極および配線の形成が容易になり
、配線系の良品率が大幅に向上した。In addition, FIG. 5 shows the present invention using a sidewall base electrode (SiCO8).
This is an example in which the present invention is applied to a type high-performance bipolar transistor. After providing an N-type buried layer in a p-type silicon layer plate, a P-doped N-type silicon layer, a B-doped P-type Sio, aGeo, and an x layer 5 are formed by molecular beam epitaxial growth.
After forming, the epitaxial growth layer is etched leaving the active region, and a polycrystalline silicon film 7 is buried through the 5i02 film 6. After doping with B at a high concentration, a SiOz film 8 for passivation (7) is formed on the surface. Then, a 5i3Na film 9 was further deposited on the entire surface. Here, a PSG film (phosphorus glass film) is used to flatten the recesses that occur on the surface.
Alternatively, a BPSG film (boron-phosphorous glass film) or non-doped 5iOzlljfilo was deposited and etched. Next, a hole for the emitter is made, and again by molecular beam epitaxial growth, Si-doped N-doped G
The aAs layer 4 was selectively formed. Then, holes for the contacts are formed after forming the emitter electrode 11, the base electrode 2. A collector electrode 3 was formed to complete the transistor. The current amplification factor of the fabricated integrated circuit transistor was about 300, and its cutoff frequency was as high as about 25 GHz. In addition, since the surface level difference caused by the base lead-out electrode is flattened by embedding the multilayer film, the formation of electrodes and wiring becomes easy, and the yield rate of the wiring system is greatly improved.
第６図は、第４図に示した集積回路用トランジスタの表
面平坦化にパッシベーション膜１０の埋込みを適用した
実施例である。このように二種類以上の薄膜を用いて素
子表面の平坦化を行なうと。FIG. 6 shows an embodiment in which embedding of the passivation film 10 is applied to planarize the surface of the integrated circuit transistor shown in FIG. In this way, two or more types of thin films are used to planarize the element surface.
表面の段差低減に加えて、厚いフィールド酸化膜を形成
する必要がなくなって基板に働く応力が小さくなり、結
晶欠陥が発生しにくくなるため、トランジスタの良品率
が大幅に向上する利点がある。In addition to reducing the level difference on the surface, there is no need to form a thick field oxide film, which reduces the stress acting on the substrate and makes crystal defects less likely to occur, which has the advantage of significantly increasing the yield rate of transistors.
本発明によれば、電流増幅率が高くかつ遮断周波数が高
い集積回路用のトランジスタを製造することができるの
で、バイポーラトランジスタおよびバイポーラ集積回路
の小型化、高性能化および高集積化に効果がある。また
、素子表面の断差が１／２以下となり、結晶欠陥の発生
が減少するのでバイポーラ集積回路の良品率が約１桁向
上した。According to the present invention, it is possible to manufacture a transistor for integrated circuits with a high current amplification factor and a high cutoff frequency, which is effective in reducing the size, performance, and integration of bipolar transistors and bipolar integrated circuits. . In addition, the deviation on the element surface is reduced to 1/2 or less, and the occurrence of crystal defects is reduced, so the yield rate of bipolar integrated circuits is improved by about one order of magnitude.
第１図および第２図は本発明の詳細な説明するための図
、第３図乃至第６図は各々本発明の実施例を示す半導体
装置の断面図である。
１・・・エミッタ電極、２・・・ベース電極、３・・・
コレクタ電極、４・・・エミツタ層、５・・・ベース層
、６，８・・・ＳｉＯ２膜、７・・・多結晶Ｓｉ膜、９
・・・５ｉａＮａ膜、１０−Ｐ Ｓ Ｇ膜またはＢＰＳ
Ｇ膜または５ｉＯｚ膜。FIGS. 1 and 2 are diagrams for explaining the present invention in detail, and FIGS. 3 to 6 are cross-sectional views of semiconductor devices showing embodiments of the present invention, respectively. 1... Emitter electrode, 2... Base electrode, 3...
Collector electrode, 4... Emitter layer, 5... Base layer, 6, 8... SiO2 film, 7... Polycrystalline Si film, 9
...5iaNa film, 10-PSG film or BPS
G membrane or 5iOz membrane.
Claims (1)
、基板に結晶シリコンを用い、その上にシリコンよりも
禁制帯幅の狭い第２の半導体層を有し、さらにその上に
シリコンよりも禁制帯幅の広い第３の半導体層を有する
ことを特徴とする半導体装置。 ２、シリコン・ゲルマニウム合金半導体を第２の半導体
層に用い、ヒ化ガリウム（ＧａＡｓ）、炭化シリコン（
ＳｉＣ）、微細晶シリコン （μＣ−Ｓｉ）のいずれかを第３の半導体層に用いるこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
。 ３、表面段差部を２種類以上の材質の薄膜を用いて平坦
化したことを特徴とする特許請求の範囲第１項乃至第２
項記載の半導体装置。[Claims] 1. In a bipolar device having a heterojunction, a substrate is made of crystalline silicon, a second semiconductor layer having a bandgap narrower than that of silicon is provided on the substrate, and a second semiconductor layer having a forbidden band width narrower than that of silicon is further provided. A semiconductor device comprising a third semiconductor layer having a wide forbidden band width. 2. A silicon-germanium alloy semiconductor is used for the second semiconductor layer, and gallium arsenide (GaAs), silicon carbide (
2. The semiconductor device according to claim 1, wherein either SiC) or microcrystalline silicon (μC-Si) is used for the third semiconductor layer. 3. Claims 1 to 2, characterized in that the surface step portion is flattened using thin films made of two or more types of materials.
1. Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1063888A JPH01187863A (en) | 1988-01-22 | 1988-01-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1063888A JPH01187863A (en) | 1988-01-22 | 1988-01-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01187863A true JPH01187863A (en) | 1989-07-27 |
Family
ID=11755752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1063888A Pending JPH01187863A (en) | 1988-01-22 | 1988-01-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01187863A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02283031A (en) * | 1989-04-24 | 1990-11-20 | Nec Corp | Hetero structure bipolar transistor |
| US5389803A (en) * | 1993-03-29 | 1995-02-14 | International Business Machines Corporation | High-gain Si/SiGe MIS heterojunction bipolar transistors |
-
1988
- 1988-01-22 JP JP1063888A patent/JPH01187863A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02283031A (en) * | 1989-04-24 | 1990-11-20 | Nec Corp | Hetero structure bipolar transistor |
| US5389803A (en) * | 1993-03-29 | 1995-02-14 | International Business Machines Corporation | High-gain Si/SiGe MIS heterojunction bipolar transistors |
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