JPH0744185B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure of a bipolar transistor having a heterojunction and a method for forming the same.

[Conventional technology]

Bipolar integrated circuits formed on a semiconductor substrate, particularly a silicon semiconductor substrate, are becoming higher in density and higher in integration and speed, and especially in an integrated circuit such as a bipolar semiconductor memory device, the degree of integration is 64 kbits or more. In addition, the access time will be 4.5nS or less and the performance will be further improved.

The high performance of bipolar integrated circuits depends largely on the speedup of bipolar transistors, especially the cutoff frequency f _T
Improvement of the carrier shortens the travel time of the carrier in the base area,
It has been reported that this can be greatly improved by reducing the area of the pn junction parasitically formed in the transistor and reducing the parasitic capacitance of the device as much as possible (1988, IEICE Spring). National Convention, PP.2-371).

Among these, the reduction of the traveling time of the carrier in the base area is
It is achieved by narrowing the base width. But,
When the base width is narrowed, the resistance of the base diffusion layer increases, so that the impurity concentration of the base diffusion layer must be increased to reduce the resistance of the base region. That is, in order to realize an ultra-high speed bipolar transistor, it is necessary that the base be extremely thin, have a high impurity concentration, and have a low resistance. However, when the base concentration is increased, the base Gummel number increases and the emitter Gummel number relatively decreases. Therefore, the impurity concentration of the emitter must be increased in order to increase the emitter Gummel number. However, if the impurity concentration of the emitter is increased, the band width is reduced (bandgap narrowing effect), the injection efficiency of electrons injected from the emitter to the base is reduced, and the current amplification factor (h _FE ) of the transistor is sufficiently increased. I will not be able to get to.

In order to solve this problem, it has recently been proposed to form an emitter-base junction using a heterojunction.
If a structure with a wide band width for the emitter and a narrow band width for the base is adopted, hole injection from the base to the emitter can be suppressed due to the difference in band width, so the injection efficiency of the electrons injected from the emitter to the base is relatively Can be made higher. Therefore, various advantages such as ensuring the current amplification factor of the bipolar transistor at a low temperature can be obtained.

As a combination of heterojunctions, there are a method using an emitter having a wide band width and a method using a base having a narrow band width. The former is, as shown in FIG. 4 (a), a material with a wide band width such as GaAs, SiC, and microcrystalline silicon as an emitter.
29 (1987 IEDM, Tech.Dig.pp186-19
3). The latter is based on MBE as shown in Fig. 4 (b).
(Molecular beam epitaxy) or MOCVD
This is a method of using a material 130 with a narrow band width such as e-mixed crystal (Spring 1988 35th Joint Lecture on Applied Physics 29aZ 12
/ I).

In particular, Si and Ge have almost the same electron affinity of 4.05 eV and 4.0 eV, respectively, and the band gaps of 1.1 e and
V is 0.66 eV. Further, it is reported that the Si-Ge mixed crystal has a band gap width intermediate between Si and Ge (Band alignments of coherently strainde Ge _X Si).
_1-X / Si heterostructures on <011> Ge _Y Si _1-Y substrat
es Applied Physical Letters 48 (8), 24 February 1
986). By combining these materials, as shown in FIG. 4 (c), Si131 is used for the emitter and Ge or Ge-Si mixed crystal layer 1 is used for the base.
32, it is possible to form a silicon heterobipolar transistor having a structure of Si133 in the collector.

In the transistor of this structure, the emitter Si
Since a pn junction is formed at the interface between 131 and the base Ge or Si-Ge mixed crystal layer 132, the energy barrier for holes becomes larger than the energy barrier for electrons,
The electrons are the main carriers that flow through the pn junction. Therefore, the emitter injection efficiency of the bipolar transistor using this heterojunction is significantly increased.

By using this heterojunction, it is possible to prevent the reduction of the emitter injection efficiency due to the reduction of the bandwidth, suppress the injection of holes from the base to the emitter, and eliminate the delay due to the holes accumulated in the emitter. This is an extremely effective means for forming a high-speed bipolar transistor by reducing the junction capacitance between the emitter and the base.

[Problems to be Solved by the Invention]

However, when Si-Ge mixed crystal (Si _1-X Ge _X ) is formed by MBE or MOCVD as a material with a narrow band width in the above-mentioned base, since Si and Si-Ge mixed crystal have different lattice constants, Si
− Due to the lattice mismatch between the Ge mixed crystal layer and the underlying Si single crystal substrate,
When a Si-Ge layer having a film thickness of a certain degree or more is deposited, there is a problem that crystal defects such as dislocations and cracks occur. Therefore, there is a problem that the Si-Ge mixed crystal layer cannot be thickly deposited on the Si substrate.

As described above, in order to increase the emitter injection efficiency, the emitter-base junction needs to have a sharp change in bandwidth. In this emitter-base junction, since it is sufficient to suppress injection of holes on the emitter side, the Si single crystal as the emitter electrode on the base Ge or Si-Ge mixed crystal layer may be thin (for example, 50- 100Å). Therefore, defect-free epitaxial growth can be performed between the base and the emitter.

However, the width of the base is to reduce the base resistance.
About 100 to 1000Å is required, and the Si-Ge mixed crystal layer needs to have a larger film thickness. In addition, it is necessary that X = 0.5 or more in order to have a sufficient (0.2 eV or more) band gap difference between the emitter and the base. Therefore, it is necessary to deposit a Si-Ge layer of 500 to 3000 Å on the Si substrate.

However, it has been reported that when a film having a composition of Si _1-X Ge _X near X = 0.5 is formed on a silicon substrate in an amount of 100 Å or more, a transition occurs in the Si _1-X Ge _X layer (SILICON MBE :
FROM STRAINED-LAYER EPITAXY TO DEVICE APPLICATIO
N: Journal of Crystal Growth 70 (1984) 444-451),
When a film with X = 0.5 or more is grown on a Si substrate of 500Å or more, misfit transition occurs in the Si-Ge mixed crystal layer due to lattice constant mismatch, and crystal defects occur in the base region. This crystal defect serves as a recombination center of carriers to lower the emitter injection efficiency and causes penetration between the emitter and collector, which is a major obstacle to obtaining normal transistor characteristics. In the base region, a technique for thickly forming a single Si-Ge mixed crystal layer that simultaneously satisfies the two requirements of increasing the Ge concentration to secure a sufficient band gap difference and securing a certain base thickness. The reality is that has not been completed yet.

An object of the present invention is to solve the above problems, to provide a base structure of a heterojunction transistor free from defects and having a high yield, and to provide a method for forming the same.

[Means for Solving the Problems]

Bipolar transistor having a heterojunction of the present invention, in the Si-Ge mixed crystal layer provided on the silicon substrate or the silicon epitaxial layer, Si-Ge mixed crystal
Formed on the silicon substrate or silicon epitaxial layer in such a manner that the concentration of germanium gradually increases toward the interface between the Si-Ge mixed crystal layer and the silicon layer that will be the emitter electrode provided on this Si-Ge mixed crystal layer. It is to be a structure.

By realizing such a structure, injection of holes is suppressed at the emitter-base junction, and the injected electrons can diffuse in the base having a substantially flat conduction band and reach the collector. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor device formed according to the first embodiment of the present invention, and FIGS. 2A to 2J are process steps for explaining the first embodiment of the present invention. It is sectional drawing of the semiconductor element shown. In the following description, the silicon oxide film will be referred to as an oxide film, and the silicon nitride film will be referred to as a nitride film for convenience.

First, on a silicon substrate 101 having a boron concentration of about 1 _× 10 ¹⁵ cm ^−3, a concentration of about 1 _× 10 ²⁰ cm ^{−3 is applied} to a partial region of the silicon substrate 101 using a well-known photolithography technique. The n ⁺ buried layer 102 that is provided is formed, and the channel stop portion 103 for electrically insulating from other elements is formed. Next, an n ⁻ epitaxial layer 104 is deposited on the silicon substrate 101. n ⁺ buried layer 102 may be formed by diffusing an impurity such as, for example, arsenic or antimony, 1 _X 10 ²⁰ cm ^-3
It only needs to have a certain concentration. Also n ^- epitaxial layer 104
May be grown while Dove impurities such as arsenic, the concentration of the impurity is 1 _X 10 ¹⁵ cm ^-3 or so, the thickness is 1~2μ
About m is enough. Next, molecular beam epitaxy (hereinafter MBE
On the n ^- epitaxial layer 104 by, for example, Si
_{The 1-X} Ge _X (X = 0.1) film 105 is grown to about 200 to 1000Å.

Next, the Si _1-X Ge _X (X = 0.3) film 106 is formed to 200 by the same MBE method.
It grows up to about 1000Å. Similarly, by MBE method, Si _1-X Ge
_{An X} (X = 0.5) film 107 and a Si _1-X Ge _X (X = 0.7) film 108 are sequentially grown to about 200 to 700 ?. The uppermost layer may have any number of layers so that a film of germanium alone is formed.
The composition of Si _1-X Ge _X may be continuously changed (Fig. 2 (a)). Furthermore, 30 to 10 are placed on the uppermost Ge-rich region.
You may grow 0Å Si. This is because this Si can be used as a part of the emitter electrode.

Next, the element isolation oxide film 109 and the electrode isolation oxide film 110 are formed in a partial region of the n ⁻ epitaxial layer 104 by a known LOCOS process. The element isolation oxide film 109 and the electrode isolation oxide film 110 may be formed in the same process, and the film thickness may be 1 to 1.5 μm. Trench element isolation may be used instead of the element isolation oxide film 109 and the electrode isolation oxide film 110. Next, an oxide film 111 and a nitride film 112 are formed by a chemical vapor deposition method, a collector contact 113 is opened, and an impurity such as phosphorus is diffused from the collector contact 113 to diffuse a high concentration impurity having n-type conductivity. The layer 114 is formed and electrically connected to the buried layer 102 (FIG. 2B).

Next, polysilicon 115 is formed and a high concentration of boron is implanted by ion implantation. Next, a nitride film 116 and an oxide film 117 are sequentially formed, and a collector-base separation and an emitter section opening are performed (FIG. 2 (c)).

Next, an oxide film is formed by a chemical vapor deposition method, only the emitter portion is opened using a well-known lithography technique, the oxide film is etched back, and an oxide film sidewall 118 is formed. The polysilicon 115 is oxidized by the subsequent oxide film etching so that the oxide film at this portion does not disappear (FIG. 2 (d)).

Next, an eaves 119 of polysilicon 115 is formed. To form the eaves 119, the nitride film 112 and the oxide film 111 are removed by etching. At the time of removing the oxide film, an oxide film containing a high concentration of boron is formed on the side surface of the polysilicon 115 by oxidation, so that the oxide film at this portion is not removed (FIG. 2 (e)).

Further, polysilicon is deposited and the eaves 119 is filled with polysilicon 120. Next, by heat treatment, the polysilicon 120
Then, boron is diffused from the polysilicon 115, the polysilicon in which boron is not diffused is removed by an alkaline solution, and the polysilicon 120 is embedded in the eaves. This heat treatment also diffuses boron into the silicon substrate, so p ⁺
The diffusion layer 121 is formed (FIG. 3 (f)).

Next, a nitride film is formed, and the nitride film sidewalls 122 are formed by etchback using a reactive ion etchback technique.
Are formed (FIG. 2 (g)).

Next, boron is ion-implanted to form a base region 12
3 is formed (Fig. 2 (h)).

Next, polysilicon 124 is formed, and n-type impurities such as arsenic are added to the polysilicon 124 at a high concentration, and heat treatment is applied to Ge having a wide band width near the surface or Si _1-X Ge _X ( X = 0.7) film 108 and polysilicon 124
Form an emitter-base junction at the interface. Next, the polysilicon 124 is patterned by a well-known photolithography technique and etching (FIG. 2 (i)).

Next, an interlayer film 125 is grown, a contact hole 126 for taking out an electrode is opened, and then an aluminum electrode 127 is formed (FIG. 2 (j)), whereby a bipolar transistor using a heterojunction between the emitter and the base is obtained. It is formed.

Next, a second embodiment of the present invention will be described with reference to FIGS. The steps of forming the n ⁺ buried layer 102, the n ⁻ epitaxial layer 104, the element isolation oxide film 109, and the electrode isolation oxide film 110 are the same as in the first embodiment. After forming the n ⁻ epitaxial layer 104, the element isolation oxide film 109, and the electrode isolation oxide film 110, germanium is introduced into the substrate surface. The introduction of germanium may be performed by forming a germanium film by chemical vapor deposition and diffusing germanium into the n ⁻ epitaxial layer 104 by heat treatment, or by implanting it by ion implantation. Further, germanium is diffused to form a Si-Ge layer 128. Since the Si-Ge layer 128 has a high germanium concentration near the surface due to thermal diffusion and has a low concentration near the n ^- epitaxial layer 104, the Si-Ge layer 128 causes crystal defects such as dislocations in the subsequent heat treatment. (Fig. 3 (a)).

Next, the base region 123 is formed by the same process as in FIGS. 2B to 2H of the first embodiment (FIG. 3B).

Next, a polysilicon 124 is formed, an n-type impurity such as arsenic is added to the polysilicon 124 at a high concentration, and a heat treatment is performed to form an emitter at the interface between the Si-Ge layer 128 having a wide band width and the polysilicon 124. Form a base bond. Next, the polysilicon 124 is patterned by the well-known photolithography technique and etching (FIG. 3C).

Through the above steps, a bipolar transistor having a heterojunction between the base and the emitter can be formed.

〔The invention's effect〕

With the heterojunction according to the present invention, a transistor having a current amplification factor of about 10 times that of a conventional bipolar transistor can be formed. Further, it is possible to form a transistor whose current amplification factor does not decrease even at low temperatures.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a bipolar transistor formed by using the method for forming a heterojunction of the first embodiment of the present invention, and FIGS. 2 (a) to (j) are the first embodiment of the present invention. 3A to 3C are explanatory views of a manufacturing process of a bipolar transistor formed by using the heterojunction of the present invention, and FIG. 3A to FIG. 3C are formed as a second embodiment of the present invention by using the heterojunction of the present invention. 4 (a) and 4 (b) are vertical cross-sectional views of a hetero-bipolar transistor for explaining the prior art, and FIG. 4 (c) is a uniform Ge region in the base region. FIG. 3 is a band diagram of a conventional silicon hetero-bipolar transistor having a Si—Ge mixed crystal layer. 101 …… Silicon substrate, 102 …… n ⁺ buried layer, 103 ……
Channel stop part, 104 …… n ^- Epi layer 104, 105 …… S
i _0.9 Ge _0.1 film, 106 …… Si _0.7 Ge _0.3 film, 107 …… Si _0.5 Ge
_0.5 film, 108 …… Si _0.3 Ge _0.7 film, 109 …… Element isolation oxide film, 110 …… Electrode isolation oxide film, 111 …… Oxide film, 112 ……
Nitride film, 113 …… Collector contact, 114 …… High concentration impurity diffusion layer, 115 …… Polysilicon, 116 …… Nitride film, 11
7 …… Oxide film, 118 …… Oxide film sidewall, 119 ……
Eaves, 120 …… polysilicon, 121 …… p ⁺ diffusion layer, 122 ……
Nitride side wall, 123 …… base region, 124 …… polysilicon, 125 …… interlayer film, 126 …… contact hole, 12
7 ... Aluminum electrode, 128 ... Si-Ge layer, 129 ... Wide band material, 130 ... Narrow band material, 131 ...
… Emitter Si layer, 132 …… Base Ge or Si-Ge layer, 133
...... Collector Si layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 29/161 29/73

Claims (3)

[Claims] 1. A mixed crystal layer of silicon and germanium on a silicon substrate or a silicon epitaxial layer having a first conductivity, and a second conductive impurity layer in the mixed crystal, and the silicon. Bipolar transistor having a silicon layer having a first conductive impurity on a mixed crystal layer of germanium and germanium, and having a heterojunction in the form of forming a pn junction at the interface between the silicon layer and the mixed crystal layer of silicon and germanium In the above, on the silicon substrate or the silicon epitaxial layer, the concentration of germanium contained in the mixed crystal of silicon and germanium gradually increases toward the interface between the outer mixed crystal layer and the silicon layer above it. A semiconductor device having a structure formed in 2. A method of forming a mixed crystal layer according to claim 1, wherein a step of chemically vapor-depositing germanium on a silicon substrate or a silicon epitaxial layer and then diffusing the germanium by thermal diffusion is used. Method for manufacturing semiconductor device 3. A mixed crystal layer of silicon and germanium as a means for forming a mixed crystal layer according to claim 1, wherein the concentration of germanium becomes higher in a silicon substrate or a silicon epitaxial layer by a molecular beam epitaxy method in an upper layer. Method for manufacturing a semiconductor device, characterized by using a step of forming