JP3332079B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of simultaneously increasing a cutoff frequency and reducing a capacitance and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to simultaneously improve the performance of a semiconductor device, in particular, to improve the cut-off frequency of a bipolar transistor and to reduce the parasitic capacitance, not only miniaturization of a simple element but also improvement of an impurity profile. At the same time as optimizing, ideas regarding the structure of the transistor are needed.

[0003] A first conventional technique for simultaneously improving the cutoff frequency and reducing the parasitic capacitance will be described. The first prior art is a technique for forming a high concentration collector by a selective ion implantation method. FIG. 32 shows a structure of a semiconductor device according to the first prior art. Here, an epitaxial silicon layer (having a concentration of about 1-3 × 10 ¹⁶
respect cm ^-3 of including phosphorus) 204, by phosphorus ion implantation, the region 1 containing phosphorus of about 1 × 10 ¹⁷ cm ^-3
16 are formed. The above technique is described in S. Konaka et al.,
“A 20 ps / G Si bipolar IC using advanced SST with
collector ionimplantation, "in Abstract of the 19
^th Conference on Solid State Devices and Materials,
Tokyo, 1987, pp. 331-334.

Next, a description will be given of a second conventional technique for improving a cutoff frequency. The second prior art is a technique for forming a high concentration collector by an epitaxial growth method. FIG. 33 shows a structure of a semiconductor device according to the second prior art. The collector region is formed from a region 146 having a high concentration (for example, including an n-type impurity of 1 to 2 × 10 ¹⁸ cm ⁻³ ) from the beginning. These technologies are described in the literature EFCrabbe et a
l., “Vertical profileoptimization of very high fr
equency epitaxial Si- and SiGe-base bipolartransis
tors, "in International Electron Devices Meeting,
1993, pp. 83-86.

[0005]

When a high performance bipolar transistor having a high cutoff frequency is formed, the CB (collector-base) depletion layer is not modulated until a high collector current density operation is performed. It is necessary to form a concentration collector.

However, when simply would increase the collector concentration, C-B capacity because rises f _T improvement is offset maximum oscillation frequency f _max is not improved.

A problem in the case where phosphorus is ion-implanted into the collector region immediately below the emitter by using the above-mentioned first prior art will be described below. For example, acceleration energy =
FIG. 34 shows the junction yield between the collector and the base with the dose of phosphorus implanted at 200 keV as a variable. Here, a non-defective product was defined as a non-defective product when a reverse current of 2.5 V was applied between the collector and the base when 10,000 transistors were connected in parallel and the leakage current value was 1 mA or less. As is clear from FIG. 34, the peak concentration of phosphorus is
When it is less than about 2 × 10 ¹⁷ cm ^-3 , 90% or more good products are obtained.

However, if phosphorus is ion-implanted so that the phosphorus concentration becomes about 3 × 10 ¹⁷ cm ⁻³ or more, crystal defects are generated and the yield rate is remarkably reduced. Phosphorus concentration is about 1
If it is × 10 ¹⁸ cm ^-3 , no good product can be obtained.

As a means for solving the problem of the deterioration of the yield, about 3
There is a method of doping phosphorus from x10 ¹⁷ cm ^-3 to about 1 x 10 ¹⁸ cm ^-3 from the beginning. However, according to the second conventional technique, the CB capacity is significantly increased. This relationship is shown in FIG. The reason why the capacitance is increased as described above is that the collector concentration is high even in a region where it is not necessary to increase the concentration (= a collector region other than immediately below the emitter).

[0010]

According to the present invention, there is provided a semiconductor device having a collector region, a base region, and an emitter region, wherein the collector region is buried at a predetermined depth from a silicon substrate surface. A first conductivity type buried layer (2) having a concentration, a groove (101) reaching the first conductivity type buried layer, an insulating film (6) buried under the side surface of the groove, and surrounded by the groove; A first concentration formed in a closed internal region and having a second concentration lower than the first concentration.
A first conductivity type single crystal layer (32) and a second first conductivity type single crystal layer formed on the first conductivity type buried layer (2) and having a third concentration lower than the second concentration. (4) the second first conductivity type single crystal layer (4), the insulating film (6), and the second first conductivity type single crystal layer (32) formed on the first first conductivity type single crystal layer (32). A first conductivity type single crystal film (33) having a concentration, wherein the base region is formed of the first conductivity type single crystal film (3).
3) a second conductivity type single crystal layer (34) formed on the surface and having a surface position at least above the insulating film (6); and the emitter region has the first concentration. And a third first conductivity type single crystal layer (36) formed on a part of the base region.

[0011] The semiconductor device of the present invention further comprises the first device.
A second first conductivity type single crystal film (31) having the first concentration is formed in an inner region surrounded by the opening (101) so as to be in contact with the conductivity type buried layer (2). It is characterized by.

Further, according to the present invention, in a semiconductor device having a collector region, a base region, and an emitter region formed on a silicon substrate, the collector region is buried at a predetermined depth from the surface of the silicon substrate. A first conductivity type buried layer (2) having a first concentration, a groove (101) reaching the first conductivity type buried layer, and a silicon oxide film (6) buried under the side surface of the groove. A first conductivity type single crystal silicon layer formed in an inner region surrounded by the groove and having a second concentration lower than the first concentration;
Formed on the first conductivity type buried layer (2);
A first conductivity type epitaxial silicon layer (4) having a third concentration lower than the second concentration, the first conductivity type epitaxial silicon layer (4), the silicon oxide film (6), and the first conductivity type; A first conductivity type single crystal silicon film (33) having the second concentration formed on the single crystal silicon layer (32), and restricting formation of a high concentration collector region to a part of a necessary region; It is characterized by doing.

Further, according to the method of the present invention for manufacturing a semiconductor device in which a collector region, a base region, and an emitter region are formed on a silicon substrate, the first device is provided at a predetermined depth from the surface of the silicon substrate. A first step of forming a first conductivity type buried layer having a concentration, and a first conductivity type epitaxial silicon layer having a third concentration lower than the first concentration on a surface of the first conductivity type buried layer. A second step of forming (4); and a third step of etching the first conductivity type epitaxial silicon layer (4) to form a groove (101) so as to reach the first conductivity type buried layer. A fourth step of forming a silicon oxide film (6) on the side surface of the groove (101); and a first step having the first concentration formed in an internal region surrounded by the groove (101). 1st conductivity type A fifth step of forming a first conductivity type single crystal silicon layer (32) having a second concentration lower than the first concentration and higher than the third concentration on the crystalline silicon film (31), and the silicon oxide film A sixth step of removing the upper portion of (6) and forming a second first conductivity type single crystal silicon film (33) having the second concentration in the exposed portion.

In the semiconductor device according to the present invention in which a collector region, a base region, and an emitter region are formed on a silicon substrate, the collector region is buried at a predetermined depth from the surface of the silicon substrate. A first conductivity type buried layer (2) having a first concentration, a groove (101) reaching the first conductivity type buried layer, a silicon oxide film (6) buried under a side surface of the groove, A second region which is formed in an inner region surrounded by the groove and is lower than the first concentration;
A first conductivity type single crystal silicon layer (9) having a concentration and a first conductivity type epitaxial silicon formed on the first conductivity type buried layer (2) and having a third concentration lower than the second concentration; A layer (4) and a first conductivity type single crystal silicon-germanium alloy film (7) formed on the first conductivity type single crystal silicon layer (9) and having the second concentration
And a first conductivity type single crystal silicon-germanium layer (13) formed on at least the silicon oxide film (6) and the first conductivity type single crystal silicon-germanium alloy film (7) and having the second concentration. ), And a single-crystal silicon region (8) for forming a first conductivity type collector lead having the first concentration and formed in a region immediately below the metal collector electrode (21-c).

Further, according to the present invention, in a semiconductor device having a collector region, a base region, and an emitter region formed on a silicon substrate (1), the collector region is located at a predetermined depth from the surface of the silicon substrate. A first conductivity type buried layer (2) having a first concentration and a second conductivity type buried layer (3) for a channel stopper having the first concentration embedded so as not to contact each other; A trench (101) reaching the buried layer, a silicon oxide film (6) buried under the side surface of the trench, and a second concentration lower than the first concentration formed in an internal region surrounded by the trench. A first conductivity type single crystal silicon layer (9) having
A third conductive layer which is formed on the surface of the silicon substrate (1) in a region where the first conductive type buried layer (2) and the second conductive type buried layer (3) are not present, and is lower than the second concentration. Concentration first conductivity type epitaxial
A silicon layer (4), a first conductivity type single crystal silicon-germanium alloy film (7) formed on the first conductivity type single crystal silicon layer (9) and having the second concentration, and at least the silicon A first conductivity type single crystal silicon film formed on the oxide film and the first conductivity type single crystal silicon-germanium alloy film having the second concentration;
The germanium layer (13) and the metal collector electrode (21-
and c) a single-crystal silicon region (8) for extracting a collector of the first conductivity type having the first concentration, which is formed in a region directly below where the second conductivity type buried layer (3) is formed. Is characterized in that an element isolation film (5) is formed.

[0016]

Further, according to the method of the present invention for manufacturing a semiconductor device in which a collector region, a base region, and an emitter region are formed on a silicon substrate, the first device is provided at a predetermined depth from the silicon substrate surface. A first step of forming a first conductivity type buried layer (2) having a concentration, and a first step having a first concentration in a part of the silicon substrate so as not to contact the first conductivity type buried layer (2). A second step of forming a two-conductivity-type buried layer (3), a surface of the first-conductivity-type buried layer (2) and the second-conductivity-type buried layer (3)
Forming a first-conductivity-type epitaxial silicon layer (4) having a third concentration lower than the second concentration on the surface of the silicon substrate in a region where no is present;
A fourth step of forming a device isolation film (5) on the second conductivity type buried layer (3); and etching the first conductivity type epitaxial silicon layer (4) to form the device isolation film (5). A fifth step of forming a groove (101) in a region where a transistor is formed inside the film (5) and so as to reach the first conductivity type buried layer;
A sixth step of forming a silicon oxide film (6) on the side surface of 1), and a second concentration lower than the first concentration and higher than the third concentration formed in an internal region surrounded by the groove (101); Forming a first-conductivity-type single-crystal silicon layer (9) having a first concentration; and forming a first-conductivity-type single-crystal silicon having the second concentration on the first-conductivity-type single-crystal silicon layer (9). An eighth step of forming a germanium alloy film (7), a ninth step of removing the upper part of the silicon oxide film (6) to expose the inside of the groove (101), and at least the exposed portion. The first conductivity type single crystal silicon;
A tenth step of forming a first conductivity type single crystal silicon-germanium layer (13) having the second concentration on the germanium alloy film (7), and a metal collector electrode (21-
a first conductivity type collector leading single crystal silicon region (8) having the first concentration in a region immediately below where c) is formed;
Characterized by having an eleventh step of forming

Further, in the semiconductor device according to the present invention in which a collector region, a base region, and an emitter region are formed on a silicon substrate, the collector region is formed on a part of the silicon substrate so as not to contact each other. A first conductivity type buried layer (2) having a first concentration, a second conductivity type buried layer (3) having a first concentration for a channel stopper, and a groove (101) reaching the first conductivity type buried layer. ), A silicon oxide film (6) buried under the side surface of the groove, and a first conductivity type single crystal silicon formed in an internal region surrounded by the groove and having a second concentration lower than the first concentration. A layer (9), formed on the surface of the first conductivity type buried layer (2) and on the surface of the silicon substrate (1) in a region where the second conductivity type buried layer (3) is not present; First conductivity type epitaxial silicon layer having less than 2 concentrations third concentration (4), is formed on the first conductive type single crystal silicon layer (9),
A first conductivity type single crystal silicon-germanium alloy film (7) having the second concentration, and a second lower concentration than the second concentration formed on the silicon oxide film (6) and in a region not directly below the emitter. A first-conductivity-type silicon-germanium film (41) having three concentrations, and a second concentration having the second concentration formed on the silicon oxide film (6) and in a region immediately below the emitter. First conductivity type silicon
The germanium film (42) and the metal collector electrode (21-
a second conductive type buried layer (3) formed in a region immediately below where c) is formed, having a first conductive type single-crystal silicon region (8) of the first conductive type having the first concentration;
A device isolation film (5) is formed thereon.

Further, according to the present invention, there is provided a semiconductor device characterized in that the element isolation film is a LOCOS oxide film.

Further, according to the present invention, there is provided a semiconductor device characterized in that the first conductivity type is n-type and the second conductivity type is p-type.

Further, according to the present invention, there is provided a semiconductor device wherein the first conductivity type is p-type and the second conductivity type is n-type.

[0022]

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein the element isolation film is a LOCOS oxide film.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein the first conductivity type is n-type and the second conductivity type is p-type.

Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein the first conductivity type is p-type and the second conductivity type is n-type.

[0026]

Further, according to the present invention, there is provided a semiconductor device characterized in that the thickness of the silicon oxide film is about half the thickness of the LOCOS oxide film.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. Here, an embodiment will be described using an npn-type vertical bipolar transistor. The present invention is applicable to a combination of the opposite conductivity types (pnp).

FIG. 1 is a longitudinal sectional view of a semiconductor device according to the first embodiment of the present invention. The crystal has a plane orientation of (100) and a resistivity of 10 to 20 Ω · cm.
P is ^- type silicon substrate 1 is used. Of course, a transistor can be formed even if the crystal plane orientation is other than this, and the resistivity is changed depending on the purpose of use.

A part of the surface of the silicon substrate has a thickness of about 2 μm.
There is an n ⁺ type buried layer 2 of m thickness. Arsenic is about 2-5 × 10 ¹⁹ cm ⁻³ in this region. Further, there is a p ⁺ type buried layer 3. This region is doped with boron, and its concentration and thickness are almost the same as those of the n ⁺ type buried layer 2.
The buried layers of different conductivity types are arranged without contacting each other.

On the surface of this buried layer and on the surface of the silicon substrate in a region where no buried layer exists, there is an n ⁻ -type epitaxial silicon layer 4. Here, phosphorus is doped, and its concentration is about 2 × 10 ¹⁶ cm ^−3.
Is about 0.7 μm. Normal LOCOS method (LOCal Oxidation of Silic)
On), the LOCOS oxide film 5 for element isolation (the thickness of the oxide film is about 0.8 μm) is formed on the p ⁺ -type buried layer 3.

A shallow trench (trench width of about 300 angstroms) 1 reaching n ⁺ type buried layer 2 is formed in a region where a transistor is formed inside the LOCOS oxide film.
01 is formed, and a silicon oxide film 6 is buried in the lower portion inside the trench.

In the internal region surrounded by shallow trench 101, there is an n ⁺ -type single-crystal silicon layer 31 in contact with n ⁺ -type buried layer 2, and further there is an n-type single-crystal silicon layer 32. .

In the region immediately below the metal collector electrode, there is an n ⁺ -type collector leading single crystal silicon region 8 in which the n ⁻ -type epitaxial silicon layer 4 is highly doped. The state up to this point is the silicon substrate 100
Call.

A silicon oxide film 10 (having a thickness of about 1000 Å) is provided on the silicon substrate 100. Further, a p ⁺ -type polycrystalline silicon 11 for base electrode (having a thickness of about 250
0 angstrom, boron concentration about 2 × 10 ²⁰ c
m- ³ ).

The silicon oxide film 10 and the p ⁺ -type polycrystalline silicon 11 for the base electrode are covered with a silicon nitride film 12 (having a thickness of about 1500 Å). P ⁺ type polycrystalline silicon 11 for base electrode
An opening 10 is formed in the silicon oxide film 10
2 are formed.

On the n ⁻ -type epitaxial silicon layer 4, the silicon oxide film 6, and the n-type single-crystal silicon layer 32 inside the opening 102, an n-type collector single-crystal silicon layer 33 is present. Further thereon, a p-type single-crystal silicon layer (= base region) 34 exists. The p-type single-crystal silicon layer (= base) 34 is connected to the p ⁺ -type polycrystalline silicon 11
Connected to.

The polycrystalline silicon 35 is covered with a silicon oxide film 17 as a side wall above the base region. Inside the opening formed by the silicon oxide film 17, there is polycrystalline silicon 18 for an emitter electrode. An emitter region 36 is formed by n-type impurity diffusion from the emitter electrode polycrystalline silicon 18. These surfaces are covered with a silicon oxide film 20. Contact openings are formed in the polycrystalline silicon for the emitter electrode, the polycrystalline silicon for the base electrode, and the collector lead-out region, and the aluminum alloy electrode 21-a for the emitter and the aluminum alloy electrode 21 for the base are formed in these openings.
-B, a collector aluminum alloy electrode 21-c is formed.

Hereinafter, the operation of the above-described semiconductor device, that is, main manufacturing steps will be described in detail with reference to vertical sectional views of respective steps. As shown in FIG. 2, p ⁻ has a (100) crystal plane and a resistivity of about 10 to 20 Ω · cm.
The mold silicon substrate 1 is used. First, an n ⁺ -type buried layer 2 and a p ⁺ -type buried layer 3 are formed in a surface region of a silicon substrate. In this method, a silicon oxide film (not shown) is formed on the silicon substrate 1 by a normal CVD method or a thermal oxidation method.

After forming a silicon oxide film of several thousand angstroms (thickness of 3000 angstroms to 7000 angstroms, for example, 5000 angstroms is described as an example), the silicon oxide film is formed by a usual photolithography method. A photoresist (not shown) is patterned on the film. Using this photoresist as a mask material, the silicon oxide film on the surface is selectively removed by an ordinary wet etching method (that is, using an HF-based solution).

Subsequently, after removing the photoresist using an organic solution, the surface of the silicon substrate inside the opening of the silicon oxide film is oxidized by 200 Å to 500 Å for alignment in the photolithography step. Arsenic is selectively introduced into the silicon substrate where the silicon oxide film is thin by ion implantation. The acceleration energy for ion implantation needs to be low enough not to penetrate the silicon oxide film serving as the mask material. The amount of the impurity to be ion-implanted is suitably set so that the impurity concentration of the buried layer is on the order of 1 × 10 ¹⁹ cm ⁻³ , and an energy of 70 keV and 5 × 10 ¹⁵ cm ⁻² are used. For example, the energy is 50 keV
At ~ 120 keV, dose amount 5 × 10 ¹⁵ to 2 × 10 ¹⁶ c
m ^-2 is suitable).

Next, in order to recover damage, activate arsenic, and push in during ion implantation, a temperature of 1000 ° C. to 1150 ° C.
C. (here, 1100 ° C., 2 hours,
Heat treatment in a nitrogen atmosphere). Thus, the n ⁺ type buried layer 2 is formed. The 5000 angstrom thick silicon oxide film is completely removed with an HF solution, and the 1000 angstrom thick silicon oxide film (50
0 Angstroms to 2500 Angstroms in thickness), patterning of photoresist, boron ion implantation (50 KeV, 1 × 10 ¹⁴ cm ⁻² ), removal of resist, heat treatment for activation (1000 ° C., 1 hour)
(In a nitrogen atmosphere) to form a channel stopper p ⁺ -type buried layer 3.

Next, after the silicon oxide film is entirely removed,
N ^- type silicon epitaxial layer 4 by a usual method
To form An appropriate growth temperature is 950 ° C. to 1050 ° C., and SiH ₄ or SiH ₂ Cl ₂ is used as a source gas. Using PH ₃ as a doping gas, 5 × 10 ¹⁵ to
Containing 5 × 10 ¹⁶ cm ^-3 of impurity (= phosphorus), thickness is suitably 0.3Myuemu～1.3Myuemu. Here, 2 ×
The thickness at a concentration of 10 ¹⁶ cm ⁻³ or less was about 0.7 μm. Thus, the n ⁻ -type silicon epitaxial layer 4 is formed on the buried layer.

Next, a LOCOS oxide film 5 for element isolation is formed. First, a thermal oxide film (not shown) of 200 Å to 500 Å is formed on the surface of the epitaxial layer 4, and a silicon nitride film (not shown) having a thickness of 7 Å is formed.
00 angstrom to 1500 angstrom is formed. Subsequently, a photoresist (not shown) is patterned by photolithography, and the silicon nitride film and the silicon oxide film are removed by dry etching. Subsequently, the silicon epitaxial layer 4 is also etched to form a groove. The depth of the groove (= depth of silicon to be etched) is suitably about half the thickness of the oxide film formed by the LOCOS method.

After removing the photoresist, the element region is oxidized while being protected by the silicon nitride film, thereby forming a silicon oxide film for element isolation, that is, a LOCOS oxide film 5. The LOCOS oxide film has an appropriate thickness reaching the buried layer 3 for channel stopper, and is, for example, 3000 Å to 10000 Å. Here, it was about 8000 angstroms. The silicon nitride film is removed by hot phosphoric acid.

Subsequently, a photoresist pattern (not shown) is formed by ordinary photolithography, and anisotropic dry etching is performed using this photoresist as a mask material (in the order of silicon oxide film etching → silicon etching). Etching). As a result, the silicon oxide film and the epitaxial silicon layer 4 in the region where there is no resist are etched, and the opening 101 is formed.

Subsequently, oxidation is performed. The oxidation rate of silicon has an impurity concentration dependency. Here, the opening 10
The conditions were such that a silicon oxide film of about 400 angstroms was formed on one side surface. At this time, a slightly thick oxide film is formed on the bottom surface of the opening 101. Here, the opening 101
It is suitable that the thickness of the silicon oxide film formed on the side surface is substantially equal to the thickness of the n-type silicon film 33 formed in a later step.

Subsequently, the silicon oxide film on the bottom surface of the opening 101 is completely removed by anisotropic dry etching. Further, since the disorder of the crystal arrangement is formed on the silicon surface during this etching, the damaged area is removed by low-power silicon etching.

Next, the step of selective crystal growth of n ⁺ -type silicon will be described with reference to FIG. As a growth condition, an LPCVD method, a gas source MBE method, or the like can be used, but here, an ultra-high vacuum chemical vapor deposition (Ultra High
A description will be given by taking a vacuum-chemical vapor deposition (UHV-CVD) method as an example.

Details of this growth method are described in a paper co-authored by the present inventor, M. Sugiyama et al., “A 1.3-μm operat
ion Si-based planar PIN photodiode with Ge absor
ption layer using strain-relaxing selective epitax
ial growth technology ", Extended abstract of the
1998 International Conference on Solid State Devic
es and Materials, Hiroshima, 1998, pp. 384-385.

Substrate temperature 605 ° C., Si ₂ H ₆ flow rate 3 scc
m, Cl ₂ flow rate 0.03 sccm is an example of the condition.
During growth, PH ₃ is also used to dope phosphorus. The flow rate of PH ₃ is about 1 × 10 ¹⁹ cm ^−3.
Condition. As a result, n ⁺
A type single crystal silicon film 31 is formed.

Referring now to FIG. 4, the stage of selective crystal growth of n-type silicon will be described. Here, the UHV-CVD method will be described as an example. Substrate temperature 6
05 ° C., Si ₂ H ₆ flow rate 3 sccm, Cl ₂ flow rate 0.03
The use of sccm is the same. However, the flow rate of PH ₃ is such that the concentration of phosphorus is about 1 × 10 ¹⁸ cm ⁻³ . At this stage, the grown crystal protrudes onto the LOCOS oxide film 5 to form a plateau, and becomes the n-type silicon film 32-a. Next, as shown in FIG. 5, when the surface is flattened by chemical mechanical polishing of silicon, abbreviated as CMP (chemical mechanical polishing) technology, an n-type silicon film 32 is obtained.

Next, referring to FIG. 6, a description will be given of a stage where the side wall of the silicon nitride film is formed in the opening where the base and the emitter are formed. An n ⁺ -type collector lead-out region 8 is formed to lower the collector resistance. First, the surface of the silicon layer 32 in which the opening is buried is slightly oxidized. At this time, an oxide film substantially equal to the silicon oxide film in a region other than the LOCOS oxide film is formed. Next, the surface is covered with a silicon oxide film 10. The film thickness is 500 angstroms to 3
2,000 angstroms is suitable, and here, 13
00 angstroms. This silicon oxide film 1
At 0, a photoresist pattern (not shown) is formed by ordinary photolithography, and phosphorus is doped into the collector lead-out region by ion implantation using this photoresist as a mask material.

That is, phosphorus is accelerated at an acceleration energy of 100K.
Ion implantation is performed under the conditions of eV and a dose of 5 × 10 ¹⁵ cm ⁻² . After the removal of the photoresist, a heat treatment for activating the implanted phosphorus and recovering the damage due to the ion implantation is performed at 900.
Rapid heat treatment by lamp heating in nitrogen atmosphere at 5 ℃
(Rapid Thermal Annealing: RTA treatment). The silicon substrate 100 is configured as described above.

Next, undoped polysilicon is deposited by low pressure chemical vapor deposition (LPCVD). The thickness of the polysilicon is 1500 angstroms to 3500
Angstroms was suitable, here 2500 Angstroms. Boron is ion-implanted into the polysilicon. The implantation energy is low enough not to penetrate the polysilicon, and the dose needs to be high enough so that the impurity concentration becomes about 1 × 10 ²⁰ cm ⁻³ . Here, 10 KeV, 1 × 10 ¹⁶ c
m ^-2 . Next, after patterning the photoresist, unnecessary polysilicon is removed by dry etching. Thus, the polysilicon 11 for the p ⁺ type base electrode is formed.
Is formed. These entire surfaces are covered with a silicon nitride film 12 having a thickness of about 1500 angstroms by LPCVD. Openings are formed in the silicon nitride film 12 and the base electrode polysilicon 11 by ordinary photolithography and anisotropic dry etching, and the photoresist is subsequently removed. After depositing the silicon nitride film by the LPCVD method, the silicon oxide film 10 is exposed by etching back by the anisotropic dry etching method by the thickness of the silicon nitride film deposited immediately before.

Next, the stage immediately before the base formation will be described with reference to FIG. Subsequently, the silicon oxide film 10 is laterally etched with an HF-based solution to expose the lower surfaces of the n ⁻ -type collector epitaxial silicon layer 4, the n-type silicon layer 32, and the base electrode polysilicon 11. FIG. Silicon oxide film 10
The exposed dimension of the base electrode polysilicon by the lateral etching must be at least longer than the thickness of the intrinsic base to be formed in the future. The reason for determining the dimensions in this way is that (1) if the etching dimension in the lateral direction is smaller than the base film thickness, the resistance of this connection part will be as large as the resistance of the intrinsic base. (2) Even if the etching size in the lateral direction is larger than the thickness of the polysilicon for the base electrode, the current does not decrease because the current flows through the graft base region near the intrinsic base. Is caused to decrease. Here the graft
The base refers to a region between the base electrode polysilicon and the epitaxially grown base.

Since the size of the side etch may be smaller than the thickness of the base electrode polysilicon, the lower surface of the base electrode polysilicon 11 is exposed by about 2,000 angstroms here. At the same time as this etching, the upper part of the silicon oxide film 6 burying the shallow trench 101 is removed.

Next, the collector forming step will be described with reference to FIG. FIG. 8 is a cross-sectional view at the stage when the collector is formed by the selective crystal growth method. Here, as the growth conditions, a UHV / CVD method will be described as an example. An example of the condition is a substrate temperature of 605 ° C. and a flow rate of Si ₂ H _{6 of 3} sccm. The growth film is doped with phosphorus (about 1 × 10 ¹⁸ cm).
^-3 ). At this time, an n-type polycrystalline Si film 35-a is formed from the lower surface of the base electrode polysilicon protruding portion toward the silicon collector layer 4 constituting the collector region.

On the other hand, silicon collector layers 4 and 3
2, an n-type single-crystal Si film 33 is formed on the exposed portion of the shallow trench groove where the silicon oxide film 6 is removed. At this time, even if facets are generated, there is practically no problem. The grown film thickness is about 30 nm.

Next, the collector forming step will be described with reference to FIG. Subsequently, the n-type polycrystalline Si film 35-a formed on the lower surface of the p ⁺ -type polysilicon 11 is doped with boron at a high concentration (this boron is diffused from the p ⁺ -type polysilicon 11). Then, a heat treatment is performed to form ap ⁺ -type polycrystalline Si film 35-b.

Next, the base forming step will be described with reference to FIG. Subsequently, an intrinsic base is formed by a selective epitaxial growth method. Intrinsic base layer 34
Consists of a 70 nm thick Si layer. This Si layer is composed of two layers, and the thickness of the layer is 40 nm (boron is 5 × 10
¹⁸ cm ^-3 ) and a 30 nm Si layer thereon (boron 5
× 10 ¹⁷ cm ^-3 ) present. During this growth, the surface of the p-type polycrystalline Si layer 35-b is simultaneously placed on the surface of the p-type polycrystalline Si layer 35-b.
(The polycrystals 35-b and 35-c are collectively referred to as a p-type polycrystal Si layer 35 hereinafter).

When all the growth is completed, the base 34
Contacts the p-type polycrystalline Si layer 35. A side wall 17 made of a silicon oxide film is formed on the side surface of the opening by depositing a silicon oxide film by LPCVD and anisotropic etching. Arsenic-doped polysilicon is reduced by about 2
Deposit 500 angstroms. Further, the polysilicon is patterned by photolithography and anisotropic dry etching. Thus, the polysilicon 18 for the n ⁺ -type emitter electrode is formed. Heat treatment (for example,
1030 ° C., 10 seconds), arsenic is diffused from the polysilicon for the emitter electrode into the intrinsic base 34 region, and n
^{A +} type single crystal emitter region 36 is formed.

Subsequently, the entire wafer is covered with a silicon oxide film 20 having a thickness of about 8000 angstroms.
The surface of the insulating film is planarized by CMP (chemical mechanical polishing). Furthermore, polysilicon 1 for the emitter electrode is formed by photolithography and anisotropic dry etching.
8, an opening reaching the base electrode polysilicon 11 and the collector lead-out region 8 is formed. After the photoresist is removed, sputtering of an aluminum alloy, patterning of the photoresist, and patterning by dry etching form the semiconductor device of FIG.

Next, a second embodiment of the present invention will be described with reference to the drawings. Here, an embodiment will be described using an npn-type vertical bipolar transistor. Note that, as in the first embodiment, the conductivity type (pn
It is also applicable to the combination of p).

FIG. 11 is a plan view of a semiconductor device according to a second embodiment of the present invention, showing a layout of a vertical npn bipolar transistor. FIGS. 12 and 13 are AA 'of FIG. The figure shows a line sectional view and a line BB 'line sectional view. Here, the LOCOS end, the polycrystalline silicon for the base electrode, the contact opening for the emitter electrode, the contact opening for the base electrode, the contact opening for the collector electrode,
Is shown.

In FIG. 12, an n ⁺ -type buried layer 2 and a p ⁺ -type buried layer 3 are provided in a part of the silicon substrate 1. The buried layers of different conductivity types are arranged without contacting each other. In FIG. 13, the plane orientation of the crystal is (100).
And p ⁻ whose resistivity is 10 to 20 Ω · cm.
The mold silicon substrate 1 is used. Of course, a transistor can be formed even if the crystal plane orientation is other than this, and the resistivity is changed depending on the purpose of use. On a part of the surface of the silicon substrate, there is an n ⁺ -type buried layer 2 in a region having a thickness of several μm. Further, there is a p ⁺ type buried layer 3. The buried layers of different conductivity types are arranged without contacting each other.

On the surface of this buried layer and on the surface of the silicon substrate in a region where no buried layer is present, there is an n ⁻ -type epitaxial silicon layer
The LOCOS oxide film 5 for element isolation formed by the S method
It is formed in contact with the p ⁺ type buried layer 3. An opening (shallow trench) 101 is formed in a region where a transistor is formed inside the LOCOS oxide film 5, and a silicon oxide film 6 is buried in the opening 101.

An n-type single crystal silicon 9 and an n-type single crystal silicon / germanium 7 are present in an inner region surrounded by the shallow trench 101. In the region immediately below the metal collector electrode, there is an n ⁺ -type collector drawing single-crystal silicon region 8 in which the n ⁻ -type epitaxial silicon layer 4 is heavily doped. The state so far is referred to as a silicon substrate 200.

The silicon oxide film 10 is on the silicon substrate 200. Further, in a partial region on the silicon oxide film, there is a p ⁺ -type polycrystalline silicon 11 for a base electrode. These silicon oxide film 10 and p ⁺ -type polycrystalline silicon 11 for the base electrode are covered with a silicon nitride film 12. An opening 101 is formed in a partial region inside the p ⁺ -type polycrystalline silicon 11 for the base electrode. An opening 102 is formed in the silicon oxide film 10 at a position spread by an equal distance from the opening.

On the n ⁻ -type epitaxial silicon layer 4 and the n-type single-crystal silicon-germanium 7 inside the opening 101, there is provided a single-crystal silicon-germanium layer 13 for an n-type collector, and A single crystal silicon-germanium alloy base having a gradient Ge composition and a region 14 composed of single crystal Si are present thereon. Here, the gradient Ge composition is a profile in which the Ge concentration decreases toward the surface.

The single-crystal silicon-germanium alloy base region 14 is formed through a composite film 15 of a polycrystalline silicon-germanium alloy film and a polycrystalline Si film through a p ⁺ for base electrode.
Connected to the polycrystalline silicon 11. Above the base region, the polycrystalline silicon-germanium alloy film 15 is covered with a silicon oxide film 17 as a side wall. In the trench formed by the silicon oxide film 17, there is polycrystalline silicon 18 for an emitter electrode. An emitter region 19 is formed by n-type impurity diffusion from polycrystalline silicon 18 for the emitter electrode. These surfaces are covered with a silicon oxide film 20. Openings for contact are formed in the polycrystalline silicon for the emitter electrode, the polycrystalline silicon for the base electrode, and the collector lead-out region, respectively. The base contact opening 104 has an emitter aluminum alloy electrode 21-a, and the opening 1
A base aluminum alloy electrode 21-b is formed in 02, and a collector aluminum alloy electrode 21-c is formed in the collector contact opening 103.

Next, the steps of manufacturing the above-described semiconductor device according to the second embodiment will be described in detail with reference to vertical sectional views of the main steps. In FIG. 14, similarly to the first embodiment described above, having a (100) crystal plane,
A p ^- type silicon substrate 1 having a resistivity of about 10 to 20 Ω · cm is used. First, an n ⁺ -type buried layer 2 and a p ⁺ -type buried layer 3 are formed in a surface region of a silicon substrate.

Next, after the silicon oxide film is entirely removed,
N ^- type silicon epitaxial layer 4 by a usual method
To form Here, the thickness at a concentration of 2 × 10 ¹⁶ cm ⁻³ or less was about 0.5 μm.

Next, a LOCOS oxide film 5 for element isolation is formed as in the first embodiment. Locos oxide film 5
Is appropriate to reach the channel stopper buried layer 3, which is about 6000 angstroms here. The silicon nitride film is removed by hot phosphoric acid.

In FIG. 15, a photoresist pattern (not shown) is subsequently formed by ordinary photolithography, and this photoresist is used as a mask material.
Perform anisotropic dry etching (silicon oxide film etching → silicon etching). As a result, the silicon oxide film and the epitaxial silicon layer 4 in the region where there is no resist are etched, and the opening 101 is formed.

In FIG. 16, oxidation is continued. The speed of the silicon oxide film depends on the impurity concentration. Here, the conditions are such that a silicon oxide film of about 300 Å is formed on the side surface of the opening 101. At this time, a slightly thick oxide film is formed on the bottom surface of the opening 101. Here, it is suitable that the thickness of the silicon oxide film formed on the side surface of the opening 101 is substantially the same as the thickness of the silicon-germanium film 13 formed in a later step.

In FIG. 17, subsequently, the silicon oxide film on the bottom surface of the opening 101 is completely removed by anisotropic dry etching. Further, since the disorder of the crystal arrangement is formed on the silicon surface during this etching, the damaged area is removed by low-power silicon etching.

In FIG. 18, the growth conditions are LPC
Although a VD method, a gas source MBE method and the like are also possible, a UHV / CVD method will be described here as an example. Substrate temperature 6
05 ° C., Si ₂ H ₆ flow rate 3 sccm, Cl ₂ flow rate 0.03
sccm is an example of the condition. During growth, PH ₃ is also used to dope phosphorus. The flow rate of PH ₃ is set so that the concentration is about 1 × 10 ¹⁹ cm ⁻³ . Opening 1
An n ⁺ -type silicon film is formed on the bottom of the substrate 01.

Referring to FIG. 19, the UHV / CVD method will be described as an example. It is the same that the substrate temperature is 605 ° C., the flow rate of Si ₂ H _{6 is 3} sccm and the flow rate of Cl _{2 is} 0.03 sccm. However, the concentration of phosphorus is about 1 × 10 ¹⁸ cm
The flow rate of PH ₃ is ^-3 .

In FIG. 20, the UHV / CV
Using method D, substrate temperature 605 ° C., Si ₂ H ₆ flow rate 3 sc
cm, GeH ₄ flow rate ₂ sccm, Cl ₂ flow rate 0.03 sc
The use of cm is the same. However, if the concentration of phosphorus is
The flow rate of PH ₃ is about 1 × 10 ¹⁸ cm ⁻³ .
At this stage, the grown crystal protrudes on the LOCOS oxide film to form a plateau. If the SiGe alloy layer is too thick, crystal defects will occur. Therefore, the final remaining film thickness (for example, in FIG. 21) is desirably equal to or less than the critical thickness, for example, 200 Å or less.
In order to increase the thickness, a profile that gradually increases the Ge concentration toward the surface is also desirable.

In FIG. 21, the surface is flattened by a silicon-based CMP technique. Thereafter, as shown in FIG. 22, an N ⁺ -type collector lead-out region 8 is formed to reduce the collector resistance. In the first embodiment, the silicon oxide film is oxidized here, but since the SiGe alloy film is not uniformly oxidized, the surface is first covered with the silicon oxide film 10. The film thickness is suitably from 1000 Å to 3000 Å, in this case 2,000 Å. Here, steps are originally formed in the silicon oxide film 10 inside and outside the opening 101, but in the drawing, the shape is described with the same film thickness and no steps. A pattern of a photoresist is formed on the silicon oxide film 10 by ordinary photolithography, and phosphorus is doped by ion implantation using the photoresist as a mask material.

That is, phosphorus is accelerated at an acceleration energy of 100K.
Ion implantation is performed under the conditions of eV and a dose of 5 × 10 ¹⁵ cm ⁻² . After the removal of the photoresist, a heat treatment for activating the implanted phosphorus and recovering the damage due to the ion implantation is performed at 900.
RTA treatment in a nitrogen atmosphere at 5 ° C. for 5 minutes. The silicon substrate 200 is configured as described above.

After that, polysilicon is deposited. Here, it was 2500 angstroms. Boron is ion-implanted into the polysilicon. Here, 10 Ke
V was 1 × 10 ¹⁶ cm ⁻² . Next, after patterning the photoresist, unnecessary polysilicon is removed by dry etching. In this manner, as shown in FIG. 23, P ⁺ type base electrode polysilicon 11 is formed. The entire surface is covered with a silicon nitride film 12 of about 1500 angstroms by LPCVD. Openings are formed in the silicon nitride film 12 and the base electrode polysilicon 11 by ordinary photolithography and anisotropic dry etching, and the photoresist is subsequently removed.

As shown in FIG. 24, the silicon nitride film 12
Then, the silicon oxide film 10 is exposed by etching back by the thickness of the silicon nitride film deposited immediately before by anisotropic dry etching.

In FIG. 25, subsequently, the silicon oxide film 10 is laterally etched with an HF-based solution.
Epitaxial silicon layer 4 for collector, silicon
Germanium layer 7 and polysilicon 11 for base electrode
The opening 102 is formed by exposing the lower surface of the substrate. The dimension in which the silicon for the base electrode is exposed by laterally etching the silicon oxide film 10 is at least longer than the thickness of the intrinsic base to be formed in the future. Further, this side etch dimension may be shorter than the thickness of the base electrode polysilicon. Here, the lower surface of the base electrode polysilicon 11 is exposed by a dimension of about 1500 angstroms. At the same time as this etching, the upper part of the silicon oxide film 6 burying the shallow trench 101 is removed.

FIG. 26 shows an intermediate stage of forming a part of the collector and the intrinsic base by the selective crystal growth method. Here, the UHV / CVD method will be described as an example of the growth conditions. The substrate temperature is 605 ° C., the flow rate of Si ₂ H ₆ is ₃ sccm, and the flow rate of GeH _{4 is 2} sccm. The growth film is doped with phosphorus. At this time, an n-type polycrystalline SiGe film 15a is formed from the lower surface of the protruding portion of the base electrode polysilicon 11 toward the silicon collector layer 4 constituting the collector region.

On the other hand, an n-type single crystal SiGe alloy film 13 is formed on the exposed portion of the silicon collector layer 3. The Ge concentration was about 10%. At this time, even if facets are generated, there is practically no problem. The grown film thickness is about 2
5 nm. Of course, it is possible to increase the film thickness within a range in which no defect occurs by a heat treatment in a later step.

At this time, an undoped polycrystalline SiGe film is simultaneously formed on the lower surface of the p ⁺ -type polysilicon. This polycrystalline film is heat-treated in order to add boron at a high concentration to form a p ⁺ -type polycrystalline SiGe film.

In FIG. 27, subsequently, an intrinsic base layer (p ⁺ -type single crystal silicon-germanium alloy base region having a gradient Ge composition) 14 is formed by selective epitaxial growth. The intrinsic base layer 14 is composed of two layers, and is composed of a P ⁺ -type SiGe layer (lower layer) and a p-type Si layer (upper layer) having a gradient Ge profile. Ge
An example of a profile, a boron concentration profile as an impurity, and a film thickness thereof will be described. It has a profile in which the Ge concentration in SiGe decreases linearly from 10% to 0% towards the surface, and its layer thickness is 40 nm.
It does not contain Ge. That is, there is a 30 nm layer made of pure Si. Both layers contain 5 × boron
10 ¹⁸ cm ^-3 has been added.

In FIG. 28, side walls 17 made of a silicon oxide film are formed on the side surfaces of the opening by depositing a silicon oxide film by LPCVD and anisotropically etching. FIG.
At 9, a 2,500 Å phosphorous doped polysilicon is deposited by LPCVD. Further, the polysilicon is patterned by photolithography and anisotropic dry etching. Thus, the polysilicon 18 for the n ⁺ -type emitter electrode is formed. Heat treatment (for example, 930 ° C., 10 seconds) is performed, and phosphorus is diffused from the polysilicon for the emitter electrode to the region of the intrinsic base layer 14 to form the n ⁺ -type single-crystal emitter region 19.

Subsequently, the entire wafer is covered with a silicon oxide film 20 having a thickness of about 3000 angstroms.
Further, an opening reaching the polysilicon 18 for the emitter electrode, the polysilicon 11 for the base electrode, and the collector lead-out region 9 is formed by photolithography and anisotropic dry etching. After the removal of the photoresist, sputtering of an aluminum alloy and patterning by photoresist and dry etching form a semiconductor device as shown in FIG.

Next, a third embodiment will be described with reference to FIG. An n ^- type SiGe 41 is grown, and phosphorus is ion-implanted only into a region immediately below the emitter later to form an n-type SiGe 42. As an example of the phosphorus implantation conditions, the acceleration energy was 200 KeV and the dose was 4 × 10 ¹² cm ⁻² .

Next, a fourth embodiment will be described. This embodiment has a structure (not shown) in which the portion of the n-type single crystal silicon / germanium alloy film 7 of the second embodiment is replaced with an n-type single crystal silicon film. Other parts are the same as those of the second embodiment. By doing so, the thickness of the SiGe film can be reduced, so that the margin of heat treatment for the occurrence of defects due to lattice mismatch can be increased.

[0094]

According to the present invention, in order to operate the transistor to a high current density, the region where the impurity concentration of the collector is high has a minimum area, so that the CB capacitance can be reduced. At the same time, an effect that high current density operation is possible and that the non-defective rate of the CB junction does not decrease is obtained. This effect will be described below using specific numerical values. FIG. 31 shows data exemplifying the effect of the present invention. FIG. 31 shows the yield rate of the junction and the junction capacitance of the transistor of the present invention as a function of the collector concentration just below the emitter.

The non-defective rate of the junction is as follows: the concentration is 1 × 10 ¹⁸ cm
Even if the concentration is increased to ^{-3, the} non-defective rate does not decrease. This is a significant improvement over the remarkable reduction in the yield rate of the prior art in which the concentration of the collector is increased by selectively ion-implanting phosphorus. This improvement in the non-defective rate can also be achieved by the second prior art in which phosphorus is added at a high concentration from the beginning when epitaxially growing the collector region.

However, according to the present invention, the capacity can be reduced. The reason is that this feature is achieved because the high concentration collector region is formed by an epitaxial growth method only in a part of the region immediately below the region where the emitter is formed.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a longitudinal sectional view at a stage where a silicon surface at a bottom of an opening 101 is removed.

FIG. 3 is a longitudinal sectional view of a stage of selective crystal growth of n ⁺ -type silicon.

FIG. 4 is a longitudinal sectional view at the stage of selective crystal growth of n-type silicon.

FIG. 5 is a longitudinal sectional view at the stage of n-type silicon planarization.

FIG. 6 is a vertical cross-sectional view at a stage where side walls of a silicon nitride film are formed in openings where bases and emitters are formed.

FIG. 7 is a longitudinal sectional view of a stage immediately before formation of a base.

FIG. 8 is a longitudinal sectional view of a collector forming stage.

FIG. 9 is a longitudinal sectional view of a collector forming stage.

FIG. 10 is a longitudinal sectional view of a base forming stage.

FIG. 11 is a plan view of a semiconductor device according to a second embodiment of the present invention, showing a layout of a vertical npn bipolar transistor.

FIG. 12 is a sectional view taken along line AA ′ of FIG. 11;

FIG. 13 is a sectional view taken along line BB ′ of FIG. 11;

FIG. 14 is a longitudinal sectional view of a stage where a LOCOS oxide film is formed.

FIG. 15 is a longitudinal sectional view at a stage where silicon is etched.

FIG. 16 is a longitudinal sectional view of a stage where a silicon surface is oxidized.

FIG. 17 is a longitudinal sectional view of a stage where a silicon surface is oxidized.

FIG. 18 is a longitudinal sectional view of a stage of selective crystal growth of n ⁺ -type silicon.

FIG. 19 is a longitudinal sectional view at the stage of selective crystal growth of n-type silicon.

FIG. 20 is a longitudinal sectional view of a stage of selective crystal growth of n-type silicon / germanium.

FIG. 21 is a longitudinal sectional view showing a stage of flattening n-type silicon / germanium.

FIG. 22 is a longitudinal sectional view of a stage of forming a collector lead-out region.

FIG. 23 is a longitudinal sectional view of a stage of forming a collector lead-out region.

FIG. 24 is a longitudinal sectional view at a stage where a side wall of a silicon nitride film is formed in an opening.

FIG. 25 is a longitudinal sectional view of a stage immediately before formation of a base.

FIG. 26 is a longitudinal sectional view of a collector forming stage.

FIG. 27 is a longitudinal sectional view of a base forming stage.

FIG. 28 is a longitudinal sectional view of a base forming step.

FIG. 29 is a longitudinal sectional view of an emitter formation stage.

FIG. 30 is a longitudinal sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 31 is a diagram showing the yield rate and junction capacitance of a semiconductor device according to the present invention, with the phosphorus concentration immediately below the emitter as a variable.

FIG. 32 is a longitudinal sectional view according to an embodiment of a conventional semiconductor device.

FIG. 33 is a longitudinal sectional view according to another embodiment of a conventional semiconductor device.

FIG. 34 is a diagram showing the yield rate of the semiconductor device shown in FIG. 31 using the ion implantation dose of phosphorus as a variable.

FIG. 35 is a diagram of the junction capacitance of the semiconductor device shown in FIG. 32;

[Explanation of symbols]

Reference Signs List 1 p ⁻ type silicon substrate 2 n ⁺ type buried layer 3 p ⁺ type buried layer for channel stopper 4 n ⁻ type single crystal silicon (= n ⁻ type single crystal silicon for collector) 5 locos oxide film 6 silicon oxide inside trench groove Film 7 n-type single-crystal silicon-germanium alloy film 8 n ⁺ -type single-crystal silicon region for extracting a collector 9 n-type single-crystal silicon film 10 silicon oxide film 11 p ⁺ -type polycrystalline silicon for base electrode 12 silicon nitride film 13 n-type Single crystal silicon / germanium layer for collector 14 Intrinsic base layer 15 Polycrystalline silicon / germanium alloy film 17 Silicon oxide film 18 Polycrystalline silicon for emitter electrode 19 n ⁺ type single crystal Si emitter region 20 Silicon oxide film 21-a Aluminum for emitter Alloy electrode 21-b Aluminum alloy electrode for base 21-c Selector aluminum alloy electrode 31 n ⁺ type single crystal silicon layer 32 n-type single-crystalline silicon layer 33 n-type single crystal silicon layer 34 p-type single crystal silicon layer (= base) 35 p-type polycrystalline silicon layer 36 n ⁺ -type single Crystal silicon layer (= emitter) 100, 200 Silicon substrate 101, 102, 103, 104 Opening

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-131039 (JP, A) JP-A-5-299429 (JP, A) JP-A-3-132040 (JP, A) JP-A-9-99 181089 (JP, A) JP-A-10-289912 (JP, A) JP-A-7-147287 (JP, A) JP-A-5-267317 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 21/331 H01L 21/205 H01L 29/737

Claims (19)

(57) [Claims] 1. A semiconductor device having a collector region, a base region, and an emitter region, wherein the collector region is buried at a predetermined depth from a surface of a silicon substrate and has a first concentration of a first conductivity type. Layer, a groove reaching the first conductivity type buried layer, an insulating film buried under the side surface of the groove, and a second concentration lower than the first concentration formed in an internal region surrounded by the groove. A first first-conductivity-type single-crystal layer having a first concentration and a second first-conductivity-type single-crystal layer formed on the first-conductivity-type buried layer and having a third concentration lower than the second concentration; A second conductive type single crystal layer having the second concentration formed on the second first conductive type single crystal layer, the insulating film, and the first first conductive type single crystal layer; The base region is formed on the first conductivity type single crystal film. A second conductivity type single crystal layer having a surface position at least above the insulating film, wherein the emitter region has the first concentration and is formed on a part of the base region. A semiconductor device having a third first conductivity type single crystal layer formed thereon. 2. The method according to claim 1, wherein a second first conductivity type single crystal film having the first concentration is formed in an internal region surrounded by the opening so as to be in contact with the first conductivity type buried layer. The semiconductor device according to claim 1, wherein: 3. A semiconductor device having a collector region, a base region, and an emitter region formed on a silicon substrate, wherein the collector region is buried at a predetermined depth from the surface of the silicon substrate. A first conductivity type buried layer having: a groove reaching the first conductivity type buried layer; a silicon oxide film buried under a side surface of the groove; and an inner region surrounded by the groove; First
A first conductivity type single crystal silicon layer having a second concentration lower than the concentration, and a first conductivity type epitaxial silicon layer formed on the first conductivity type buried layer and having a third concentration lower than the second concentration. And a first conductivity type single crystal silicon film having the second concentration formed on the first conductivity type epitaxial silicon layer, the silicon oxide film, and the first conductivity type single crystal silicon layer, A semiconductor device wherein formation of a high-concentration collector region is limited to a part of a necessary region. 4. A method of manufacturing a semiconductor device in which a collector region, a base region, and an emitter region are formed on a silicon substrate, wherein a first concentration having a first concentration is located at a predetermined depth from the surface of the silicon substrate. A first step of forming a one conductivity type buried layer, and a second step of forming a first conductivity type epitaxial silicon layer having a third concentration lower than the first concentration on a surface of the first conductivity type buried layer A third step of etching the first conductivity type epitaxial silicon layer to form a groove so as to reach the first conductivity type buried layer; and a fourth step of forming a silicon oxide film on a side surface of the groove. And the first step formed in an internal region surrounded by the groove.
A fifth step of forming a first conductivity type single crystal silicon layer having a second concentration lower than the first concentration and higher than the third concentration on the first first conductivity type single crystal silicon film having a concentration; A sixth step of removing the upper portion of the silicon oxide film to expose the inside of the trench; and forming a portion on the exposed portion, the first conductivity type epitaxial silicon layer and the first conductivity type single crystal silicon layer. A method of manufacturing a semiconductor device, comprising: a seventh step of forming a second first conductivity type single crystal silicon film having the second concentration. 5. A semiconductor device having a collector region, a base region, and an emitter region formed on a silicon substrate, wherein the collector region is buried at a predetermined depth from the surface of the silicon substrate. A first conductivity type buried layer having a concentration, a groove reaching the first conductivity type buried layer, a silicon oxide film buried below a side surface of the groove, and an inner region surrounded by the groove, The first
A first conductivity type single crystal silicon layer having a second concentration lower than the concentration, and a first conductivity type epitaxial silicon layer formed on the first conductivity type buried layer and having a third concentration lower than the second concentration. A first conductivity type single crystal silicon-germanium alloy film formed on the first conductivity type single crystal silicon layer and having the second concentration; at least the silicon oxide film and the first conductivity type single crystal silicon A first conductivity type single crystal silicon-germanium layer formed on a germanium alloy film and having the second concentration, and formed in a region immediately below a metal collector electrode;
A semiconductor device comprising a single-crystal silicon region for extracting a collector of a first conductivity type having the first concentration. 6. A semiconductor device having a collector region, a base region, and an emitter region formed on a silicon substrate, wherein the collector region is buried at a predetermined depth from the surface of the silicon substrate so as not to contact each other. A first conductivity type buried layer having a first concentration; a second conductivity type buried layer for a channel stopper having the first concentration; a groove reaching the first conductivity type buried layer; A silicon oxide film buried in the first region and an inner region surrounded by the trench,
A first-conductivity-type single-crystal silicon layer having a second concentration lower than the concentration, and a surface of the first-conductivity-type buried layer and a surface of the silicon substrate in a region where the second-conductivity-type buried layer does not exist. A first conductivity type epitaxial silicon layer having a third concentration lower than the second concentration, and a first conductivity type single crystal silicon formed on the first conductivity type single crystal silicon layer and having the second concentration. A germanium alloy film, a first conductivity type single crystal silicon-germanium layer formed on at least the silicon oxide film and the first conductivity type single crystal silicon-germanium alloy film and having the second concentration, and a metal collector Formed in the area immediately below the electrode is formed,
A semiconductor device, comprising: a first conductivity type single-crystal silicon region for leading a collector having the first concentration; and an element isolation film formed on the second conductivity type buried layer. 7. A method for manufacturing a semiconductor device in which a collector region, a base region, and an emitter region are formed on a silicon substrate, wherein a first concentration having a first concentration is located at a predetermined depth from the surface of the silicon substrate. A first step of forming a buried layer of one conductivity type; and a second step of forming a buried layer of a second conductivity type having a first concentration on a part of the silicon substrate so as not to contact the buried layer of the first conductivity type. And a first conductivity type epitaxial layer having a third concentration lower than the second concentration on the surface of the silicon substrate in the surface of the first conductivity type buried layer and in a region where the second conductivity type buried layer does not exist. A third step of forming a silicon layer, a fourth step of forming an element isolation film on the second conductivity type buried layer, and etching the first conductivity type epitaxial silicon layer. A fifth step of forming a groove in a region where a transistor is formed on the inner side of the element isolation film and reaching the first conductivity type buried layer; and a silicon oxide film on a side surface of the groove. A sixth step of forming; and a first step formed in an internal region surrounded by the groove.
A seventh step of forming a first conductivity type single crystal silicon layer having a second concentration lower than the concentration and higher than the third concentration, and a second step having the second concentration on the first conductivity type single crystal silicon layer. An eighth step of forming a one-conductivity-type single-crystal silicon-germanium alloy film, a ninth step of removing an upper portion of the silicon oxide film to expose the inside of the trench, and at least the exposed portion and the first A tenth step of forming a first conductivity type single crystal silicon-germanium layer having the second concentration on the conductivity type single crystal silicon-germanium alloy film; and forming the first conductivity type single crystal silicon-germanium layer in a region immediately below a metal collector electrode. A method for manufacturing a semiconductor device, comprising: an eleventh step of forming a single-crystal silicon region for leading a collector of a first conductivity type having a single concentration. 8. A semiconductor device having a collector region, a base region, and an emitter region formed on a silicon substrate, wherein the collector region is formed on a part of the silicon substrate so as not to contact with each other. A first conductivity type buried layer having a concentration and a second conductivity type buried layer having a first concentration for a channel stopper; a groove reaching the first conductivity type buried layer; and silicon buried under a side surface of the groove. An oxide film, formed in an internal region surrounded by the trench,
A first-conductivity-type single-crystal silicon layer having a second concentration lower than the concentration, and a surface of the first-conductivity-type buried layer and a surface of the silicon substrate in a region where the second-conductivity-type buried layer does not exist. A first conductivity type epitaxial silicon layer having a third concentration lower than the second concentration, and a first conductivity type single crystal silicon formed on the first conductivity type single crystal silicon layer and having the second concentration. A germanium alloy film; a first first conductivity type silicon-germanium film having a third concentration lower than the second concentration formed on the silicon oxide film and in a region not directly below the emitter; A second first conductivity type silicon-germanium film having the second concentration formed on the oxide film and in a region immediately below the emitter; Is formed in a region immediately below that is,
A semiconductor device comprising: a first conductivity type single crystal silicon region for leading a collector having the first concentration; and an element isolation film formed on the second conductivity type buried layer. 9. The semiconductor device according to claim 6, wherein said element isolation film is a LOCOS oxide film. 10. The semiconductor device according to claim 1, wherein said first conductivity type is n-type and said second conductivity type is p-type.
10. The semiconductor device according to 6, 8, or 9. 11. The semiconductor device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.
10. The semiconductor device according to 6, 8, or 9. 12. The semiconductor device according to claim 3, wherein the first conductivity type is an n-type. 13. The semiconductor device according to claim 3, wherein the first conductivity type is a p-type. 14. The method according to claim 7, wherein the element isolation film is a LOCOS oxide film. 15. The method according to claim 4, wherein the first conductivity type is an n-type. 16. The method according to claim 4, wherein the first conductivity type is a p-type. 17. The semiconductor device according to claim 7, wherein the first conductivity type is an n-type and the second conductivity type is a p-type.
5. The method for manufacturing a semiconductor device according to item 4. 18. The method according to claim 7, wherein the first conductivity type is p-type, and the second conductivity type is n-type.
5. The method for manufacturing a semiconductor device according to item 4. 19. The semiconductor device according to claim 9, wherein a thickness of said silicon oxide film is about half of a thickness of said LOCOS oxide film.