JPH03248535A - Bipolar transistor element - Google Patents

Abstract

PURPOSE:To obtain a power transistor which can control a large current without increasing the area of a chip by forming the depth of a base layer of a region not formed with an emitter layer shallower than that of the base layer of a region formed with the emitter layer. CONSTITUTION:Since a base layer 5a of a region not formed with an emitter layer 3 is formed shallower than a base layer 5b of other part, the resistance of the layer 5a disposed to the layer 3 is raised. Thus, it becomes the same state as the state in which a ballast resistor is inserted between a base.emitter junction and a base electrode 2, and a current is not concentrated at a specific unit transistor. It is not necessary to provide a diffused layer for the resistor in the layer 5a to the layer 3 separately from the layer 5a. Thus, it is not necessary particularly to provide a diffused layer for the resistor, and a large current bipolar transistor element having a multiemitter structure in which a current is not concentrated at the specific emitter layer can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bipolar transistor device, and more particularly to a bipolar transistor device for large currents having multiple emitters.

(Prior Art) A bipolar type large current power transistor generally has a multi-emitter structure in order to increase the effective area of the emitter.

FIG. 2 shows a cross-sectional view of a conventional large current bipolar transistor.

This bipolar transistor consists of a p-type base layer (depth, about 20 μm) 5 formed in a selected region near the upper surface of an n-type silicon substrate 7, and a plurality of p-type base layers (depth, about 20 μm) formed in a predetermined region of the base layer 5. n-type emitter layer (depth, approximately 10 μm
) 3. In FIG. 2, the depth of the base layer is designated C and is substantially constant within the substrate 7.

An emitter electrode 1 is formed on the emitter layer 3, and the emitter layer 3 and the emitter electrode 1 are electrically connected. Further, a base electrode 2 is formed on a predetermined region other than the region where the emitter layer 3 is formed, and the base layer 5 and the base electrode 2 are electrically connected. This bipolar transistor is an assembly of unit transistors in which a large number of unit transistors are connected in parallel, and can thereby control a large current.

(Problems to be Solved by the Invention) However, conventional bipolar transistors have a problem in that current may concentrate and flow to a specific unit transistor among the plurality of unit transistors described above.

To solve this problem, a bipolar transistor in which a ballast resistance layer is provided between each emitter layer 3 has been developed. FIG. 3 shows a cross-sectional view of this improved bipolar transistor.

The ballast resistance layer 8 is an n
This is a type impurity diffusion layer, and is usually formed at the same time as the n-type emitter layer 3 is formed. With this ballast resistance layer 8,
This prevents current from flowing concentratedly into a specific unit transistor.

However, in order to form the ballast resistance layer 8, the distance between each emitter layer 3 must be increased.
A problem arises in that the area occupied by the element increases.

In addition, in order to obtain a desired current amplification factor, it is necessary to set the depth of the emitter layer 3 to a predetermined value. The depth of the ballast resistance layer 8 is determined by the depth of the emitter layer 3 to be formed. Therefore, the degree of freedom in designing the resistance value of the ballast resistance layer 8 is reduced.

If the formation of the ballast resistance layer 8 and the formation of the emitter layer 3 are formed in separate steps, the number of manufacturing steps will increase, resulting in problems of lower manufacturing yield and increased manufacturing cost.

The present invention has been made in order to solve the above problems, and its purpose is to provide a multilayer multilayer system that does not require the provision of a diffusion layer for the ballast resistor, and in which the current does not concentrate on a specific emitter layer. An object of the present invention is to provide a large current bipolar transistor element having an emitter structure.

(Means for Solving the Problems) A bipolar transistor element of the present invention includes a silicon substrate of a first conductivity type, and a base layer of a second conductivity type formed in a selected region near the upper surface of the silicon substrate. a plurality of emitter layers of a first conductivity type formed within the base layer; an emitter electrode formed on each of the emitter layers and electrically connected to the emitter layer; formed on a region of the layer where the emitter layer is not formed;
a base electrode electrically connected to the base layer, the depth of the base layer in the region where the emitter layer is not formed is equal to the depth of the base layer in the region where the emitter layer is formed. shallower than the depth, thereby achieving the above objective.

(Example) The present invention will be described below with reference to Examples.

As shown in FIG. 1, the bipolar transistor element of this embodiment includes a p-type base layer 5 formed in a selected region near the top surface of an n-type silicon substrate 7, and A plurality of n-type emitter layers (depth, 1
This is a multi-emitter type bipolar transistor element having a diameter of 0 μm) 3. The bipolar transistor of this embodiment is a vertical npn transistor in which the n-type substrate 7 functions as a collector.

The base layer 5 of this embodiment has a shallow base layer 5a in a region where the emitter layer 3 is not formed and a deep base layer 5b in a region where the emitter layer 3 is formed. In FIG. 1, the depth of the base layer 5a is indicated by A, and its value is approximately 10 μl. Further, the depth of the base layer 5b is indicated by B, and its value is approximately 20 μm.

An emitter electrode 1 is formed on the emitter layer 3, and the emitter layer 3 and the emitter electrode 1 are electrically connected. Further, a base electrode 2 is formed on a predetermined region other than the region where the emitter layer 3 is formed, and the shallow base layer 5a and the base electrode 2 are electrically connected.

As described above, in this embodiment, the shallow base layer 5a in the region where the emitter layer 3 is not formed is shallower than the base layer 5b in other parts (because the emitter layer 3 is formed).
The resistance of the base layer 5a located therebetween is high.

Therefore, the state is similar to the state in which a ballast resistor is inserted between the base-emitter junction and the base electrode 2, and current does not concentrate and flow to a specific unit transistor. Further, since there is no need to provide a diffusion layer for ballast resistance in the base layer 5a between the emitter layers 3 separately from the base layer 5a, the distance between the emitter layers 3 can be reduced compared to the conventional one. I was able to do that.

In this embodiment, the sheet resistance of the shallow base layer 5a is approximately 10
The resistance value of the base layer 5a can be set to an arbitrary value by controlling the impurity concentration, depth, etc. of the shallow base layer 5a.

Next, a method for forming the base layer 5 having the above structure will be explained.

First, after depositing an oxide film containing impurities (first doped oxide film) on the entire surface of the n-type silicon substrate 7,
Using conventional photolithography and etching techniques, the doped oxide layer was patterned so that it remained over the areas where the emitter layer 3 was to be formed.

After this, a drive-in process is performed at 1200°C or higher for about 10 hours to form a deep base layer 5 with a depth of about 20 μm.
b was formed.

After removing the first doped oxide film, a second doped oxide film was formed to form a shallow base layer 5a, and the second doped oxide film was patterned into a predetermined pattern. Next, a shallow base layer 5a having a depth of about 10 μm was formed by a drive-in process at 1200° C. or higher for about 5 hours.

In this manner, by performing the diffusion process twice, it was possible to form the base layer 5 having a shallow portion and a deep portion.

In this embodiment, the shallow base layer 5a is formed by diffusion from a doped oxide film, but it may be formed using another method, for example, an ion-blating method. According to the ion blating method, the shallow base layer 5a
can be easily formed uniformly within the surface of the substrate.

In this way, by forming the shallow base layer 5a in a step different from the step of forming the deep base layer 5b,
The resistance of the shallow base layer 5a could be set to any value.

Furthermore, although this embodiment uses a substrate-type npn transistor, the present invention also applies to other types of npn transistors or
It can also be applied to pnp) transistors.

(Effects of the Invention) According to the present invention, the depth of the base layer in the region where the emitter layer is not formed is shallower than the depth of the base layer in the region where the emitter layer is formed. Since it functions as a ballast resistor, there is no need to newly provide a diffusion layer serving as a ballast resistor between the plurality of emitter layers. Therefore, the limited area of the chip can be used effectively.

Therefore, it is possible to provide a power transistor that can control large currents without increasing the chip area.

Furthermore, since the step of forming the shallow portion of the base layer can be performed independently of the step of forming the emitter layer, there is an advantage that there is a high degree of freedom in designing the shallow portion of the base layer that functions as a ballast resistor.

4. Figure 1 is a cross-sectional view showing an embodiment of the present invention, Figure 2 is a cross-sectional view showing a conventional example, and Figure 3 is a cross-sectional view showing an improved example of the conventional example shown in Figure 2.

1... Emitter electrode, 2... Base electrode, 3...
Emitter layer, 5... Base layer, 5a... Shallow base layer, 5b... Deep base layer, 7... Silicon base L
8...Ballast resistance layer.

that's all

Claims (1)

[Claims] 1. A silicon substrate of a first conductivity type, a base layer of a second conductivity type formed in a selected region near the upper surface of the silicon substrate, and a base layer formed within the base layer. a plurality of emitter layers of a first conductivity type, an emitter electrode formed on each of the emitter layers and electrically connected to the emitter layer, and the emitter layer of the base layer. a base electrode formed on a region where the emitter layer is not formed and electrically connected to the base layer, the depth of the base layer in the region where the emitter layer is not formed is equal to a bipolar transistor element.