JP2501317B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: (a) TECHNICAL FIELD The present invention relates to a semiconductor device in which a diffusion layer is formed in a semiconductor substrate such as a silicon wafer and a contact hole is opened in an oxide film on the substrate to form an electrode. It relates to a manufacturing method.

(B) Prior art General npn planar monolithic bipolar
An example of a method of manufacturing a transistor is shown in FIGS. 2 (a) to (d) and (e).

First, as shown in FIG. 2A, a silicon wafer 1
A base region 3 made of p-type silicon is diffused and formed in a central upper layer of the collector region 2 made of n-type silicon in FIG.
A silicon oxide film 4 is covered thereover. Next, FIG. 2 (b)
As shown in FIG. 5, an emitter forming hole 5 having a width S ₁ narrower than the upper surface of the base region 3 is opened in the central portion of the silicon oxide film 4 by photoetching. Subsequently, as shown in FIG. 2C, impurities such as phosphorus are diffused from the emitter formation hole 5 into the silicon wafer 1 to form an emitter region 6 made of n-type silicon under the emitter formation hole 5. , And the silicon oxide film 4 covers it. Then, as shown in FIG. 2D, the silicon oxide film 4 is formed.
Contact holes 7 and 8 are formed on the emitter region 6 and the base region 3 on both sides thereof by photoetching, and electrodes (not shown) are formed there to complete the transistor. However, in this manufacturing method, the emitter formation hole 5 and the contact holes 7 and 8 must be separately opened by two photomasks.
As shown in FIG. 6E, when a large misalignment occurs in the mask alignment (deviation: d in FIG. 2E), the contact hole 7 for forming the emitter electrode is formed in the base region 3.
There is a risk of opening up to the top and short-circuiting between the base and emitter. Therefore, in order to prevent such a short circuit, it is necessary to preset a mask margin (width: l shown in FIG. 2D) having a sufficient width to compensate for the mask alignment deviation d. It was Therefore, in this general transistor manufacturing method, in order to provide the mask margin 1 having a sufficient width, the stripe width of the emitter region 6 (that is,
Figure 2 (b) to indicate the emitter formation hole 5 of width: had to widen the S _1). However, the stripe width S ₁ of the emitter region 6 affects the high frequency characteristics of the transistor.

High frequency transistors are used as a guide for showing high frequency characteristics.
FM (Figure of Merit) is used, and the larger this value, the better the characteristics. This FM is expressed as follows when the base collector time constant is r _bb ′ · C _c and the maximum cutoff frequency is f _T.

Therefore, in order to obtain a high-frequency transistor with good characteristics, it is necessary to reduce the base-collector time constant r _bb ′ · C _c , assuming that the maximum cutoff frequency f _T is constant. If the stripe width of the emitter region 6 is S, the collector capacitance per unit area is C _o , and the base resistance is r _o ,
FM is represented as follows.

That is, in order to improve the high frequency characteristics of the high frequency transistor, it is necessary to make the emitter stripe width S as narrow as possible, and make the base resistance r _o and collector capacitance _Co as small as possible.

However, in the general transistor manufacturing method shown in FIGS. 2A to 2D, the emitter stripe width S ₁ must be widened as described above, and the mask margin l is set as l _1. Therefore, l ₂ becomes large and the base area increases as a result, resulting in an increase in collector capacitance C _o, which is unsuitable for a method of manufacturing a high frequency transistor.

Therefore, the conventional high-frequency transistor manufacturing method employs the wash emitter type shown in FIGS. 3 (a) to (d) and (e).

In the method of manufacturing the wash emitter type, as shown in FIG. 3A, first, a base region 3 made of p-type silicon is diffused and formed on a central upper layer of a collector region 2 made of n-type silicon in a silicon wafer 1. Then, the silicon oxide film 4 is covered thereover. Next, as shown in FIG. 3B, an emitter forming hole 5 having a width S ₂ is opened in the central portion of the silicon oxide film 4 by photoetching. Subsequently, as shown in FIG. 3C, impurities such as phosphorus are diffused from the emitter forming hole 5 into the silicon wafer 1 to form an emitter region 6 made of n-type silicon under the emitter forming hole 5. . Then, as shown in FIG. 3 (d), contact holes 8 and 8 are formed by photoetching on the base regions 3 on both sides of the silicon oxide film 4, and finally, electrodes (not shown) are formed in the holes 5 and 8, respectively. The high frequency transistor is completed by forming. In this case, the emitter forming hole 5 is also used as a contact hole for forming an emitter electrode, but the emitter region 6 is not only below the emitter forming hole 5 but also laterally to some extent during diffusion formation. spread, in fact, since the direction of the width S ₂ stripe width S ₂ of the emitter region 6 than the emitter formation hole 5 widens slightly short-circuited with the base region 3 be formed an electrode on the emitter formation hole 5 There is no danger of

In this wash emitter type manufacturing method, since the emitter forming hole 5 can also be used as a contact hole for forming an emitter electrode, a large mask like the case where the contact hole 7 is overlapped with the emitter forming hole 5 is formed. The margin l becomes unnecessary, and even if there is some deviation in mask alignment when the contact hole 8 for forming the base electrode is opened, the base-emitter is hardly short-circuited. Therefore, it is not necessary to make the width S ₂ of the emitter hole 5 as wide as the width S ₁ of the emitter forming hole 5 shown in FIG. 2B, so that the stripe width S ₂ of the emitter region 6 can be made narrow. it can.
However, even when such a manufacturing method is adopted, when the mask alignment deviation d as shown in FIG. 3 (e) occurs, the base electrode is located at an unbalanced position with respect to the emitter region 6. Since it is formed, the base resistance r _o per unit area of the transistor increases. Further, as shown in FIG. 3 (e), it is necessary to provide at least a margin l ₃ for preventing a short circuit with the emitter region even if there is a mask alignment deviation for opening the base contact holes 8,8. , Was still insufficient to reduce the base resistance r _o . Therefore, in the conventional method for manufacturing a high-frequency transistor of the wash-emitter type, although the stripe width S ₂ of the emitter region 6 can be narrowed, the base resistance r _o per unit area cannot be sufficiently reduced. There has been a limit in improving the high frequency characteristics of the high frequency transistor.

(C) Object of the Invention The object of the present invention has been made in view of the above circumstances, and a single photomask simultaneously opens a diffusion layer forming hole and an electrode forming contact hole. By doing so, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of eliminating the mask alignment deviation and improving the high frequency characteristics.

Another object of the present invention is to provide a method of manufacturing a semiconductor device in which the number of times of mask alignment is reduced, the accuracy of each pattern is increased, and the high frequency characteristics can be improved.

Another object of the present invention is to provide a method of manufacturing a semiconductor device, which can prevent the photoresist film from being burned and can easily increase the dose amount.

Another object of the present invention is to provide a method of manufacturing a semiconductor device in which the breaking of electrodes is prevented.

(D) Configuration and Effect of the Invention In the method of manufacturing a semiconductor device of the present invention, a hole forming step of simultaneously opening a plurality of holes to be opened in an oxide film on a semiconductor substrate, and forming a thin oxide film on the semiconductor substrate. And a step of forming an oxide film, covering the semiconductor substrate with a first photoresist film,
A first photoresist film pattern forming step of opening a photoresist film above a part of the holes opened in the oxide film to be larger than this hole; and etching a part of the opened photoresist film. A first etching step of removing the thin oxide film; a first photoresist film removing step of removing the first photoresist film; and an impurity ion implantation from the surface of the semiconductor substrate to form the thin oxide film. An ion implantation layer forming step of forming an ion implantation layer in the semiconductor substrate below the removed hole, and covering the semiconductor substrate with a second photoresist film,
A second photoresist film pattern forming step of leaving a photoresist film above the ion-implanted layer and forming a photoresist film having a larger opening than the other holes in holes other than the hole of the ion-implanted layer; A second etching step of removing the thin oxide film by etching an opening of the photoresist film, a second photoresist film removing step of removing the second photoresist film, and each hole And an electrode forming step of forming electrodes, respectively.

The ion-implanted layer is annealed in the subsequent thermal diffusion process to become an impurity diffusion layer. Also, the thin oxide film will be removed for all holes during the electrode formation process, but in the case of a MOS transistor,
It can be used as an oxide film between the semiconductor and the electrode without removing it as it is.

If the method for manufacturing a semiconductor device of the present invention is configured as described above, holes for impurity diffusion and electrode formation can be simultaneously formed in one region of p-type and n-type regions with one photomask. , It is not necessary to set the mask margin, the stripe width of the impurity diffusion region can be sufficiently narrowed, and the electrode position does not become unbalanced due to the mask alignment deviation. You can prevent it from rising. For this reason, this semiconductor device manufacturing method prevents the reduction in product yield and contributes to the improvement of the high frequency characteristics of the transistor, and is an extremely effective invention particularly in the manufacturing of the high frequency transistor. In addition, according to the present invention, since there is no mask alignment deviation when forming holes,
A reliable device can be obtained without the oxide film being displaced and the semiconductor surface of the semiconductor substrate being left exposed. Further, since the accuracy of mask alignment at the time of removing the thin oxide film is relaxed, labor saving and high efficiency of the manufacturing process can be achieved. In addition, since the oxide film near each hole has a stepped shape, disconnection of the electrode is prevented.
In addition, since the impurity ions are implanted without the photoresist film, even if the dose amount is increased to increase the carrier concentration, the photoresist film is not burned by the ion implantation.

(E) Example Hereinafter, a case where the present invention is applied to manufacture of a high frequency transistor will be described as an example.

1 (a) to (i) are respectively the first of the present invention.
4A to 4C are cross-sectional views of a silicon wafer in each step of manufacturing the high-frequency transistor that is the example of FIG.
The transistor is shown in a simplified and schematic form.

First, as shown in FIG. 1A, a silicon wafer 1
A base region 3 made of p-type silicon is diffused and formed in a central upper layer of the collector region 2 made of n-type silicon in FIG.
A silicon oxide film 4 is covered thereover. This base area 3
Is 10000Å on the collector region 2 made of n-type silicon.
A silicon oxide film 4 having a thickness of about 3 is formed, and a central portion of the silicon oxide film 4 is opened by photoetching,
It is formed by diffusing impurities such as boron into the silicon wafer 1 by vapor diffusion or thermal diffusion after ion implantation from the opening. FIG. 1 (a) shows that
A state in which the opening is covered with a silicon oxide film 4 having a thickness of about 6000Å is shown. Next, as shown in FIG. 1B, three holes 9 are formed at equal intervals in the center and both sides of the silicon oxide film 4 in this embodiment. This hole 9
Are opened by photoetching, and the figure shows the state after the photoresist film is removed. This step corresponds to the hole forming step described in claim 1. Then, first
As shown in FIG. 3C, a thin silicon oxide film 4 is formed on the silicon wafer 1. This thin silicon oxide film 4
Are formed by chemical vapor deposition or thermal oxidation to have a thickness of about 2000Å at each hole 9 portion. This step corresponds to the oxide film forming step described in claim 1. Subsequently, as shown in FIG. 1 (d), the silicon wafer 1 is covered with a photoresist film 10, and only the photoresist film 10 on the central hole 9 is slightly widened by photoetching. At this time, the photoresist film 10
Since the mask alignment of the photomask for the opening of the hole does not need to reach the holes 9 and 9 on both sides, the width of this opening is appropriately larger than the width of the central hole 9. In particular, it does not require a particularly high precision, and no inconvenience occurs even in normal work. This step corresponds to the first photoresist film pattern forming step described in claim 1. Then, first
As shown in FIG. 2E, the silicon oxide film 4 in the portion where the photoresist film 10 is opened is etched. On this occasion,
By controlling the etching amount to about 3000 Å, the surface of the silicon wafer 1 is exposed only in the hole 9 part, and the silicon oxide film 4 is left in the surroundings about 3000 Å. This process corresponds to the first etching process described in claim 1. Subsequently, as shown in FIG. 1F, the remaining photoresist film 10 is removed. This step corresponds to the first photoresist film removing step described in claim 1. After that, ion implantation is performed from the substrate surface to form an emitter region 6 which is an ion implantation layer in the substrate below the opening of the photoresist film. This process corresponds to the ion implantation layer forming process described in claim 1. Thereafter, as shown in FIG. 1 (g), the silicon wafer 1 is covered with a photoresist film 10, and then the other photoresist film 10 is removed leaving only the photoresist film 10 on the central hole 9. . This step corresponds to the second photoresist film pattern forming step described in claim 1. At this time, since the mask alignment of the photomask for removing the photoresist film 10 does not need to reach the removed portion up to the central hole 9, the width of the remaining photoresist film 10 is changed to the width of the central hole 9. If you make it an appropriate size that is wider than
No special high precision mask alignment is required, and no inconvenience occurs even in normal work. In the embodiment, not only the central hole 9 but also the photoresist film 10 on the surrounding silicon oxide film 4 is left with a sufficient space. This is to reduce the MOS capacitance by leaving the silicon oxide film 4 in the wiring portion as thick as possible. Subsequently, as shown in FIG. 1H, the silicon oxide film 4 in the portion where the photoresist film 10 is opened is etched. At this time, the etching amount is 3000
By controlling to about Å, holes 9 on both sides
The silicon surface is exposed only in the part, and the periphery of the silicon oxide film 4 is left in a state of about 3000 Å. The figure shows a state where the photoresist film 10 is removed thereafter. This step corresponds to the second etching step described in claim 1. This step corresponds to the second photoresist film removing step described in claim 1. And
As shown in FIG. 1 (i), an electrode 11 is formed in each hole 9 to complete the high frequency transistor. This electrode 11 is formed by patterning a photoresist film on the silicon wafer 1, vacuum-depositing aluminum on the photoresist film, and then removing the photoresist film. The electrode 11 may be formed by partially removing aluminum vacuum-deposited on the entire silicon wafer 1 by photoetching, other than the embodiment. The process shown in FIG. 1 (i) corresponds to the electrode forming process described in claim 1.

In the method of manufacturing the high-frequency transistor of this embodiment configured as described above, the central hole 9 serves both as the emitter forming hole and the contact hole for forming the emitter electrode, and the contact hole for forming the base electrode is on both sides. Since the holes 9 are simultaneously formed by one photomask, it is not necessary to set a mask margin, and the emitter-base electrode interval can be reduced. As a result, the base resistance r _o can be made small, and the stripe width of the emitter region 6 can be made sufficiently narrow like the stripe width S ₂ of the emitter region 6 in the case of the method of manufacturing the wash emitter type high frequency transistor. Further, with respect to the mask alignment, the position of the base electrode does not become imbalanced with respect to the emitter region 6 due to the mask alignment deviation, so that the base resistance r _o per unit area is prevented from increasing. You can Therefore, the formula expressing the FM, In, since the stripe width S of the emitter region 6 can be narrowed and the base resistance r _o per unit can be reduced, the value of FM can be increased and the high frequency characteristics can be improved. Further, in this method of manufacturing a high-frequency transistor, the accuracy of mask alignment is relaxed, so that the manufacturing process can be labor-saving and highly efficient.

The above description has been made with an example in which the NPN bipolar transistor has one emitter stripe and two base stripes, but the same applies to the PNP transistor, and the number of emitters and base stripes is not limited to this example.

[Brief description of drawings]

1 (a) to 1 (i) are cross-sectional views of a silicon wafer in respective steps in a method of manufacturing a high frequency transistor according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are respectively, FIG. 2E is a cross-sectional view of the silicon wafer in each step of the general transistor manufacturing method, and FIG. 2E shows the silicon wafer when the mask alignment in the step of FIG. 2D in the same transistor manufacturing method is misaligned. Sectional views, FIGS. 3 (a) to 3 (d) are sectional views of a silicon wafer at respective steps in a conventional method for manufacturing a high-frequency transistor, and FIG. FIG. 3 is a cross-sectional view of the silicon wafer when the mask alignment is misaligned in the process of FIG. 3D. 1 ... Silicon wafer (semiconductor substrate), 4 ... Silicon oxide film (oxide film), 6 ... Emitter region (diffusion layer), 9
…… Hall, 10 …… Photoresist, 11 …… Electrode.

Claims (1)

(57) [Claims] 1. A hole forming step of simultaneously opening all holes to be opened in an oxide film on a semiconductor substrate, an oxide film forming step of forming a thin oxide film on the semiconductor substrate, and a step of forming a thin oxide film on the semiconductor substrate. A first photoresist film which is covered with a first photoresist film and has a photoresist film above a part of the holes formed in the oxide film, which is larger than this hole;
A photoresist film pattern forming step, a first etching step of removing the thin oxide film by etching the opening of the photoresist film, and a first photoresist removing the first photoresist film. A resist film removing step; an ion implantation layer forming step of implanting impurity ions from the surface of the semiconductor substrate to form an ion implantation layer in the semiconductor substrate below the hole from which the thin oxide film has been removed; Is covered with a second photoresist film, and a photoresist film having a larger opening than the other holes is formed in the holes other than the holes of the ion implantation layer while leaving the photoresist film above the ion implantation layer. Second
A photoresist film pattern forming step, a second etching step of removing the thin oxide film by etching the opening of the photoresist film, and a second photoresist removing the second photoresist film. A method of manufacturing a semiconductor device, comprising: a resist film removing step; and an electrode forming step of forming an electrode in each hole.