JPH0626217B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

With the miniaturization of high frequency semiconductor devices, the electrode width on the semiconductor chip has become a problem.

A conventional technique of this type is disclosed in, for example, JP-A-61-158176.
In the publication, an opening for each electrode is formed in an insulating film that covers the surface of a semiconductor substrate, and the electrode is provided so as to cover the periphery thereof.

4 (a) to 4 (i) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional semiconductor device and a method of manufacturing the same, and FIG. 5 is an electrode corresponding to FIG. 4 (i). FIG.

As shown in FIG. 4A, first, a p-type base region 35 is formed on the n-type silicon substrate 31, and then a silicon oxide film 39 is formed on the surface of the n-type silicon substrate 31.

Next, base contact and emitter openings 31b and 31e are formed by the usual photolithography technique.

Next, as shown in FIG. 4B, a polycrystalline silicon layer 38 is deposited on the surfaces of the holes 31 _b and 31 _e and the silicon oxide film 39.

Next, as shown in FIG. 4 (c), the polycrystalline silicon layer 38
First photoresist layer 3 until its surface is flat
9 is deposited.

Next, as shown in FIG. 4 (d), the first photoresist layer 3
Isotropic etching is carried out in an oxygen atmosphere until 9 is left only in the emitter openings 31 _b .

Next, as shown in FIG. 4 (e), the remaining photoresist 39
Is used as a mask to perform isotropic etching with CF ₄ + O ₂ until the thickness of the polycrystalline silicon layer 38 becomes thinner than that of the silicon oxide film 39.

Next, as shown in FIG. 4 (f), the surface of the polycrystalline silicon layer 38 in the base contact opening 31b and the peripheral surface of the silicon oxide film 39 are covered and protected by the second photoresist layer 42. .

Next, as shown by the arrow, a large amount of n-type impurities are ion-implanted to dope the polycrystalline silicon layer 38 _n in the emitter opening 31 _e with a high concentration of n-type impurities.

Next, as shown in FIG. 4 (g), the opening 3 for the emitter is formed.
The surface of the polycrystalline silicon layer 38 _n in 1 _e and the peripheral surface of the silicon oxide film 39 are covered and protected by the third photoresist layer 40.

Next, as shown by the arrow, by ion-implanting a large amount of p-type impurities, the opening 31 _b for the base contact is formed.
The polycrystalline silicon layer 38 _p therein is heavily doped with p-type impurities.

Next, as shown in FIG. 4 (h), high temperature heat treatment is performed to form an emitter diffusion layer 44 and a base contact layer 45 on the upper layer of the p-type base region 35.

Finally, as shown in FIG. 4 (i), the silicon oxide film 39
After depositing an Al layer on the surfaces of the polycrystalline silicon layers 38 _n and 38 _p , the emitter electrode 47 and the base electrode 48 are shaped and separated by a normal photolithography technique.

FIG. 5 is an electrode pattern diagram corresponding to FIG. 4 (i).

That is, FIG. 4 (i) is a sectional view taken along the line AA 'of the conductor chip corresponding to FIG.

The high frequency characteristics are improved by combining the emitter electrode 47 and the base electrode 48 in a comb shape.

[Problems to be solved by the invention]

In general, in order to improve the high frequency characteristics of high frequency transistors, the collector and
It is important to reduce the base junction capacitance.

Therefore, it is required to reduce the emitter-emitter pitch and the width of the emitter electrode and the base electrode.

In the conventional semiconductor device and the manufacturing method thereof described above, when the pitch between the emitters and the emitters is designed to be 5 μm in order to improve the recent high frequency characteristics, it is difficult to accurately align the electrode patterns, so that a short circuit between the electrodes is not generated. Also, there is a problem that a short circuit with each electrode on the contact opening is likely to occur.

It is an object of the present invention to provide a method of manufacturing a semiconductor device provided with a contact electrode which does not cause a manufacturing yield or quality problems.

[Means for solving problems]

A method for manufacturing a semiconductor device of the present invention comprises: (A) a step of selectively forming an isolation insulating layer for partitioning the element forming region on a main surface of a semiconductor substrate having an element forming region by a photolithography technique, (B) A step of forming an insulating film on the surface of the semiconductor substrate, (C) a step of forming an opening portion selectively in the element forming region by anisotropic etching in the insulating film, (D) inside the opening portion And a step of forming a metal layer that covers the insulating film, (E) a step of forming a photoresist layer that covers the surface of the metal layer, and then removing the photoresist layer other than in the openings by isotropic etching, (F) a step of forming an electrode by etching away the metal layer other than inside the opening using the photoresist layer as a mask.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (j) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG. 1 (a), a first (silicon) oxide film layer 2 having a thickness of about 50 nm is formed on the surface of an n-type silicon substrate 1.
And a first nitride film layer 3 having a thickness of about 150 nm is formed.

Next, the silicon semiconductor substrate 1 and the first nitride film layer 3 and the first oxide film layer 2 on the silicon semiconductor substrate 1 are sequentially etched and removed by a usual photolithography technique so as to surround the element formation region. Expose the part.

Next, as shown in FIG. 1 (b), the first nitride film layer 3 is used as a mask to perform high-temperature thermal oxidation until the height is the same as that of the first oxide film layer 2, so that the exposed portion of the silicon substrate 1 is exposed. The second oxide film layer 4 is formed.

Next, after removing the first nitride film layer 3 with hot phosphoric acid, p-type impurities are ion-implanted into the silicon substrate 1 from the upper surface under the conditions of an implantation voltage of 30 keV and an implantation amount of 5 × 10 ¹³ / cm ^2. The active base region 5 is formed.

Next, as shown in FIG. 1 (c), a second nitride film layer 6 having a thickness of 100 mm and a third oxide film layer 7 having a thickness of 1.4 μm are formed on the semiconductor chip.

Next, as shown in FIG. 1 (d), a base electrode pattern opening portion 11b and an emitter electrode pattern opening portion 11e are formed by a normal photolithography technique.
A polycrystalline silicon layer 8 having a thickness of 2 μm is formed.

Next, the surface of the polycrystalline silicon layer 8 is covered with a first photoresist layer 9 having a thickness of about 3 μm until the surface thereof becomes flat.

Next, as shown in FIG. 1 (e), until the first photoresist layer 9 remains only in the openings 11e for the emitter electrode pattern and the openings 11b for the base electrode pattern, Isotropic etching is performed by chemical dry etching in an O ₂ atmosphere.

Next, the polycrystalline silicon layer 8 is removed by isotropic etching with CF ₄ + O ₂ until it reaches the height of the second nitride film layer 6 to form polycrystalline silicon layers 8 _e and 8 _b .

Next, as shown in FIG. 1 (f), the polycrystalline silicon layer _8e in the emitter electrode pattern opening 11e and the silicon oxide film 7 around the polycrystalline silicon layer _8e are covered and protected by the second photoresist layer 10.

High concentration impurity into the polycrystalline silicon layer 8b of the opening portion 11 _b of the base electrode pattern by a large amount of ion implantation by then the p-type impurity from the upper surface of ^{60keV, 1 × 10 15 / cm} 2 Conditions To form a p-type polycrystalline silicon layer 8 _p .

Next, as shown in FIG. 1 (g), to cover and protect the silicon oxide film 7 of polycrystalline silicon layer 8 _b and its periphery in the opening 11 _b of the base electrode pattern in the third photoresist layer 12 .

Next, a large amount of n-type impurities are ion-implanted from the upper surface under the conditions of 60 kev and 1 × 10 ¹⁶ / cm ² to make a high concentration in the polycrystalline silicon layer 8 _e in the emitter hole 11 _e . An n-type polycrystalline silicon layer 8 _n is formed by doping.

Next, as shown in FIG. 1 (h), the emitter diffusion layer 14 and the base contact layer 15 are formed at 1000 ° C. for 20 minutes.

Next, as shown in FIG. 1 (i), an Al layer 16 having a thickness of about 1 μm is deposited on the entire surface of the semiconductor chip.

Next, a fourth photoresist layer 13 having a thickness of about 3 μm is entirely deposited on the Al layer 16 until its surface becomes flat.

Next, isotropic etching is performed in an O ₂ atmosphere until the fourth photoresist layer 13 remains in the groove of the Al layer 16 corresponding to the p-type and n-type polycrystalline silicon layers 8 _p and 8 _n. Thus, the photoresist layer 20 is removed by etching.

Next, as shown in FIG. 1 (j), Cl ₄ + O _{2 is used} until the Al layer 16 becomes thinner than the height of the third oxide film layer 7 using the photoresist layer 13 remaining in the groove of the Al layer 16 as a mask. The emitter electrode 17 and the base electrode 18 are formed by removing with isotropic etching.

FIG. 2 is an electrode pattern diagram corresponding to FIG. 1 (i).

FIG. 1 (i) shows the corresponding semiconductor chip AA 'of FIG.
It is a line sectional view.

The widths of the emitter electrode 17 and the base electrode 18 are the widths of the openings 11 _e and 11 _b provided in the second silicon oxide film 2, and the size can be reduced to 5 μm or less without the possibility of contact between adjacent electrodes.

3 (a) to 3 (f) are cross-sectional views of the semiconductor chip shown in the order of steps for explaining the second embodiment of the present invention.

The semiconductor device is a lateral Schottky diode.

As shown in FIG. 3 (a), the n-type silicon substrate 1 and the first silicon oxide film except the step of forming the p-type base region 5 from the same steps as the above-mentioned FIG. 1 (a) to (c) 2, the second silicon oxide film 4, the second nitride film 6 and the third silicon oxide film 7 are formed.

Next, as shown in FIG. 3 (b), after forming an opening 11 _o for an automic electrode pattern in the third silicon oxide film 7 by a photolithography technique, an n-type impurity is added to the silicon substrate 1 To the ohmic contact layer 20
To form.

Next, as shown in FIG. 3 (c), after forming a Schottky electrode pattern opening 11 _s between both openings 11 _o by a photolinography technique, shot on the entire surface of the semiconductor chip. A molybdenum film 21 is deposited as a key metal.

Next, as shown in FIG. 3 (d), after the molybdenum film 21 other than the opening 11 _s is removed by etching, opening 11 _s
A silicon oxide film 7 using the photoresist layer 10 _a of the periphery
Protect with coating.

Next, as shown in FIG. 3 (e), the molybdenum film 21 in the ohmic electrode pattern openings 11 _o is removed with a hydrogen peroxide-based solution.

Next, the Al layer 16 is vapor-deposited on the entire surface of the semiconductor chip.

Finally, as shown in FIG. 3 (f), the Schottky electrode 22 and the ohmic electrode 23 are formed by the same method as in the first embodiment.
To form.

In the first and second embodiments, the double insulating film is formed by stacking the first silicon oxide film 2 and the first nitride film 3, but any one of them has the same effect.

〔The invention's effect〕

As described above, according to the present invention, by forming the electrode pattern in a self-aligned manner in the opening for each electrode formed in the insulating film on the semiconductor substrate, each of the electrodes can be formed with a fine dimension equal to or higher than the resolution of the photolithography technique. By forming electrodes, short circuits between adjacent electrodes and short circuits between contact holes and different electrodes can be prevented, and the quality of semiconductor devices can be greatly improved, and the manufacturing yield is 5 μm or less between emitters and emitters. There is an effect that a high-frequency high-frequency semiconductor device manufacturing method is obtained.

[Brief description of drawings]

FIGS. 1 (a) to 1 (j) are sectional views of a semiconductor chip shown in the order of steps for explaining a first embodiment of the present invention, and FIG.
FIG. 3A is an electrode pattern diagram corresponding to FIG. 1I, FIGS. 3A to 3F are sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention, and FIG. FIG. 5 is a cross-sectional view of the semiconductor chip shown in the order of steps for explaining one example of the method for manufacturing a semiconductor device, and FIG. 5 is an electrode pattern diagram corresponding to FIG. 4 (i). 1 ... N-type silicon semiconductor substrate, 4 ... second silicon oxide film, 7 ... third silicon oxide film, 11b, 11e, 11
o, 11s …… Opening part, 4th photoresist layer, 16 …… Al
Layer, 17 ... Emitter electrode, 18 ... Base electrode, 22
...... Schottky electrode, 23 …… Ohmic electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/48 P 7738-4M 29/73

Claims (1)

[Claims] 1. A step of selectively forming an isolation insulating layer for partitioning the element forming region on a main surface of a semiconductor substrate having an element forming region by a photolithography technique, and (B) a surface of the semiconductor substrate. A step of forming an insulating film on the insulating film, (C) a step of selectively forming an opening corresponding to the element forming region in the insulating film by anisotropic etching, (D) the inside of the opening and the insulating film Forming a metal layer covering the metal layer, (E) forming a photoresist layer covering the surface of the metal layer, and then removing the photoresist layer other than in the opening by isotropic etching, (F) the And a step of forming an electrode by etching away the metal layer other than the inside of the opening using the photoresist layer as a mask.