JPH0612777B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: (a) Technical Field The present invention relates to the manufacture of a semiconductor device in which a diffusion layer is formed in a semiconductor substrate such as a silicon wafer and a contact hole is opened in an oxide film on the substrate to form an electrode. Regarding the method.

(b) Prior art General npn planar monolithic bipolar
An example of a method for manufacturing a transistor is shown in FIGS. 2 (a) to (d) and
Shown in (e).

First, as shown in FIG. 2 (a), a base region 3 made of p-type silicon is diffused and formed on a central upper layer of a collector region 2 made of n-type silicon in a silicon wafer 1, and a silicon oxide film 4 is formed on the base region 3. cover. Next, as shown in FIG. 2 (b), an emitter forming hole 5 having a width S ₁ narrower than the upper surface of the base region 3 is formed in the central portion of the silicon oxide film 4 by photoetching. Next, as shown in FIG. 2 (c), impurities such as phosphorus are diffused from the emitter formation holes 5 into the silicon wafer 1 to form the emitter formation holes 5.
An emitter region 6 made of n-type silicon is formed in the lower part of the, and a silicon oxide film 4 is covered thereover. And Fig. 2
As shown in (d), contact holes 7 and 8 are formed on the emitter region 6 of the silicon oxide film 4 and the base regions 3 on both sides of the silicon oxide film 4 by photoetching, and electrodes (not shown) are formed there. Complete the transistor.

However, in this manufacturing method, since the emitter formation hole 5 and the contact holes 7 and 8 must be separately opened by two photomasks, as shown in FIG. When a deviation (difference in FIG. 2 (e): d) occurs, the contact hole 7 for forming the emitter electrode may short-circuit to the base region 3 between the opening base and the emitter. Therefore, in order to prevent such a short circuit, a mask margin (second
It was necessary to preset the width shown in Fig. (D); l). Therefore, in this general transistor manufacturing method, in order to provide the mask margin 1 having a sufficient width, the stripe width of the emitter region 6 (that is, the width of the emitter forming hole 5 shown in FIG. 2B: S ₁ ) Had to be wide. However, the stripe width S ₁ of the emitter region 6 affects the high frequency characteristics of the transistor.

The high-frequency transistor is an F.F. M. (Figure of Merit) is used, and the larger this value, the better the characteristics. This F. M. Is expressed as follows, where r _bb ′ · C _c is the base collector time constant and _T is the maximum cutoff frequency.

Therefore, to obtain a high-frequency transistor with good characteristics,
Considering that the maximum cutoff frequency _T is constant, the base collector time constant r _bb ′ · C _c must be reduced. When the stripe width of the emitter region 6 is S, the collector capacitance per unit area is C _o , and the base resistance is r _o ,
This F. M. Is represented as follows.

In other words, in order to improve the high frequency characteristics of the high-frequency transistor is configured to narrow as possible emitter stripe width S, it is necessary to minimize base resistance r _o, the collector capacitance C _o.

However, in the general transistor manufacturing method shown in FIGS. 2A to 2D, as described above, the emitter stripe width S ₁
Must be made wider, and since a distance including the mask margin l is provided as l ₁ , the base resistance r _o is also increased. Further, since the mask margin l is provided, l ₂ is increased, resulting in an increase in the base area. Since the collector capacitance C _o also increases, it was unsuitable for a method of manufacturing a high frequency transistor.

Therefore, the conventional high-frequency transistor manufacturing method is the third method.
The washed emitter type shown in Figures (a) to (d) and (e) was used.

The manufacturing method of this washed emitter type is as follows.
As shown in FIG. 3 (a), n in the silicon wafer 1 is
A base region 3 made of p-type silicon is diffused and formed on the central upper layer of the collector region 2 made of silicon-type silicon, and the base region 3 is covered with a silicon oxide film 4. Next, as shown in FIG. 3B, an emitter forming hole 5 having a width S ₂ is opened in the central portion of the silicon oxide film 4 by photoetching. Subsequently, as shown in FIG. 3 (c), impurities such as phosphorus are diffused from the emitter forming hole 5 into the silicon wafer 1 to form an emitter region 6 made of n-type silicon under the emitter forming hole 5. . Then, as shown in FIG. 3 (d), contact holes 8 and 8 are formed on the base regions 3 on both sides of the silicon oxide film 4 by photoetching, and finally, electrodes (not shown) are formed in the holes 5 and 8, respectively. The high frequency transistor is completed by forming. In this case,
Although the emitter forming hole 5 is also used as a contact hole for forming the emitter electrode, the emitter region 6 diffuses not only below the emitter forming hole 5 but also in the lateral direction to some extent during diffusion formation. because who width S ₂ stripe width S ₂ of the emitter region 6 than the emitter formation hole 5 widens somewhat, there is no possibility for shorting the base region 3 be formed an electrode on the emitter formation hole 5.

In this wash emitter type manufacturing method, since the emitter forming hole 5 can also be used as a contact hole for forming an emitter electrode, a large mask like the case where the contact hole 7 is overlapped with the emitter forming hole 5 is formed. The margin l becomes unnecessary, and even if there is some deviation in mask alignment when the contact hole 8 for forming the base electrode is opened, the base-emitter is hardly short-circuited. Therefore, it is not necessary to make the width S ₂ of the emitter hole 5 as wide as the width S ₁ of the emitter formation hole 5 shown in FIG. 2B, so that the stripe width S ₂ of the emitter region 6 can be made narrow. it can. However, even if such a manufacturing method is adopted, when the mask alignment deviation d as shown in FIG.
To be formed into an unbalanced signal with respect to
The base resistance r _o per unit area of the transistor increases. Further, even if the mask alignment deviation for opening the base contact holes 8, 8 occurs as shown in FIG. 3 (e), it is necessary to provide at least a margin l ₃ for preventing a short circuit with the emitter region. the reduction of the base resistance r _o was still insufficient. Therefore, the conventional wash emitter type high frequency transistor manufacturing method is
While the stripe width S ₂ of the emitter region 6 may be somewhat narrower, since it is impossible to sufficiently reduce the base resistance r _o per unit area, it had resulted in limitations in improving the high frequency characteristics of the high-frequency transistor.

(c) Object of the Invention The present invention has been made in view of the above circumstances, and simultaneously uses a single photomask to simultaneously serve as a diffusion layer forming hole and an electrode forming contact hole. By forming a polysilicon coating in the hole in which the diffusion layer is formed, and forming an electrode by the lift-off method, it is possible to achieve miniaturization of the semiconductor device without requiring special mask alignment accuracy. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of improving high frequency characteristics.

(d) Configuration and effects of the invention A semiconductor device manufacturing method according to the present invention comprises an all-forming step of opening a plurality of holes in an oxide film on a semiconductor substrate, and an oxide film forming process for forming a thin oxide film on the semiconductor substrate. A step of forming a photoresist film over the semiconductor substrate and opening a photoresist film above a part of the holes opened in the oxide film, and a step of forming the photoresist film. A first etching step for removing the thin oxide film in the opened hole portion, a photoresist film removal method, a polysilicon coating forming step for forming a polysilicon coating on the semiconductor substrate, and a thin oxidation step for the holes opened in the oxide film. An impurity diffusion step of forming a diffusion layer in the semiconductor substrate below the hole where the film is removed, and an electrode film forming process of forming an electrode film on the semiconductor substrate. And a second photoresist film pattern forming step of covering the semiconductor substrate with a photoresist film and opening a photoresist film above the holes other than the hole in which the diffusion layer is formed below, and the opening of the photoresist film. A second etching step of removing the electrode film and the polysilicon film below the portion, and the oxide film is etched using the electrode film and the polysilicon film remaining in the second etching step as an etching mask,
A third etching step of etching the oxide film having a diffusion layer formed below and removing a thin oxide film of a hole portion other than the hole having a diffusion layer formed below, and after depositing an electrode material on the semiconductor substrate, A lift-off electrode forming step of forming an electrode in the hole portion where the thin oxide film is removed in the third etching step by removing the photoresist film formed in the second photoresist film pattern forming step. .

The thin oxide film formed in the oxide film forming step is
Holes other than the holes in which the diffusion layer was formed before the lift-off electrode formation step are etched and removed using the electrode film and the polysilicon coating as a mask.
In the case of an S-type transistor, it can be used as an oxide film between a semiconductor and an electrode without removing it as it is.

If the method for manufacturing a semiconductor device of the present invention is configured as described above, holes for impurity diffusion and electrode formation can be simultaneously formed in one region of p-type and n-type regions with one photomask. , it is not necessary to set a mask margin, the stripe width of the impurity diffusion region can be sufficiently narrow, further base electrode and the emitter electrode contact distance of the hole can be shortened result, it is possible to reduce the base resistance r _o Not only that, because the electrode positions do not become imbalanced due to the mask alignment deviation, it is possible to prevent the resistance between the electrodes from increasing. Further, since it is possible to prevent the side etching of the oxide film in the hole where the diffusion layer is formed by the polysilicon film, the stripe width of the impurity diffusion region can be made narrower than the possibility of causing a short circuit between different regions. can do. Further, since the electrodes are formed by the lift-off method in the holes other than the hole in which the diffusion layer is formed in the lower part, it is possible to surely perform mask alignment by the side etching of the electrode film in the second etching step without forming a photoresist again. A gap is formed between the electrodes, the photoetching step can be omitted, and the gap between the base contact hole and the emitter contact hole can be further narrowed. For this reason, this semiconductor device manufacturing method prevents a decrease in product yield and further contributes to the improvement of the high-frequency characteristics of the transistor, and is an extremely effective invention particularly in manufacturing a high-frequency transistor. Further, according to the present invention, since there is no deviation in mask alignment when forming holes, there is no possibility that the oxide film will be displaced and the semiconductor surface of the semiconductor substrate remains exposed, and a reliable element can be obtained. You can Furthermore, since mask alignment is not necessary or accuracy is reduced when removing a thin oxide film, it is possible to achieve labor saving and high efficiency in the manufacturing process.

(e) Examples Hereinafter, examples in which the present invention is applied to a method for manufacturing a high frequency transistor will be described.

1 (a) to 1 (k) are cross-sectional views of a silicon wafer in respective steps in a method of manufacturing a high frequency transistor, showing an embodiment in which the present invention is applied to an NPN transistor. It is shown in a simplified and schematic form. Of course, the present invention can be applied to a PNP transistor.

First, as shown in FIG. 1 (a), a base region 3 made of p-type silicon is diffused and formed on a central upper layer of a collector region 2 made of n-type silicon in a silicon wafer 1, and a silicon oxide film 4 is formed thereon. cover. In the base region 3, a silicon oxide film 4 having a thickness of about 10000Å is formed on the collector region 2 made of n-type silicon, and a central portion of the silicon oxide film 4 is opened by photoetching. It is formed by diffusing impurities such as boron into the silicon wafer 1 by phase diffusion or thermal diffusion after ion implantation. FIG. 1 (a) shows a state in which the opening is thereafter covered with the silicon oxide film 4 having a thickness of about 6000Å. Next, as shown in FIG. 1B, three holes 9 are formed at equal intervals in the center and both sides of the silicon oxide film 4 in this embodiment. This hole 9 is opened by photoetching, and the figure shows the state after the photoresist is removed. This step corresponds to the hole forming step described in claim 1. Next, the first
As shown in FIG. 1C, a thin silicon oxide film 4 is formed on the silicon wafer 1. This thin silicon oxide film 4 is
2000 in each hole 9 part by vapor phase growth or thermal oxidation
It is formed to have a thickness of about Å. This step corresponds to the oxide film forming step described in claim 1.
Next, as shown in FIG. 1 (d), a silicon wafer 1
The upper part is covered with a photoresist 10 and only the photoresist 10 on the central hole 9 is slightly widened by photoetching. At this time, the mask alignment of the photomask performed for the opening of the photoresist 10 is required only if the openings do not reach the holes 9 on both sides, so that the width of this opening is smaller than the width of the central hole 9. If the size is wide enough and appropriate, no special precision is required, and no inconvenience will occur even in the normal mask alignment work.
This step corresponds to the first photoresist film pattern forming step described in claim 1. Next, the first
As shown in FIG. 3E, the silicon oxide film 4 in the portion where the photoresist 10 is opened is etched. At this time, by controlling the etching amount to about 3000 Å, the silicon surface of the silicon wafer 1 is exposed only in the hole 9 part, and the silicon oxide film 4 is still around 3000 Å around it.
Make a state of remaining. This step corresponds to the first etching step described in claim 1. Continuing,
As shown in FIG. 1 (f), after removing the remaining photoresist 10, a polysilicon film 11 is formed on the silicon wafer 1. This step corresponds to the polysilicon film forming step described in claim 1. Continuing,
As shown in FIG. 1 (g), the silicon wafer 1 is covered with the photoresist 10 and only the photoresist 10 on the central hole 9 is slightly widened by photoetching to remove impurities such as phosphorus from the silicon wafer 1. The emitter region 6 is formed below the hole 9 by performing thermal diffusion after ion implantation. Incidentally, during the ion implantation, chemical vapor deposition during when there is a risk that photoresist 10 can not be cured by removing the first view and (f) and (g), the S _i O ₂ after the entire surface is deposited, Figure 1 by photoresist processing a photoresist 10 (g) may be S _i O _2. Alternatively, the step of FIG. 1 (g) is omitted, and the ion implantation is performed under the condition that the photoresist 10 is not provided under the ion implantation conditions. Further, as the polysilicon film 11 formed on the silicon wafer 1, doped polysilicon to which an impurity is added in advance is used, and thermal diffusion is directly performed from the state shown in FIG. The emitter region 6 may be formed by omitting the step g). This emitter region 6
The step of forming the impurity corresponds to the impurity diffusion step described in claim 1. Subsequently, as shown in FIG. 1 (h), an electrode film 12 is formed on the silicon wafer 1. This step corresponds to the electrode film forming step described in claim 1. Subsequently, as shown in FIG. 1 (i), the other polysilicon film 11 and the electrode film 12 are removed by photoetching, leaving only the polysilicon film 11 and the electrode film 12 on the central hole 9. The electrode film 12 left by the photo etching becomes an emitter electrode.
At this time, since the mask alignment of the photomask performed for removing the polysilicon film 11 and the electrode film 12 does not need to reach the removed portion up to the central hole 9, the remaining polysilicon film 11 and the electrode film 12 are removed. The width may be set to an appropriate size that is sufficiently wider than the width of the central hole 9, and no inconvenience occurs even if the work does not correspond to the special fine process. Also, during this photo etching,
The lateral side etching of the polysilicon film 11 and the electrode film 12 is positively utilized. In the example,
Not only on the central hole 9 but also on the surrounding silicon oxide film 4
The upper polysilicon film 11 and the electrode film 12 are also left with a sufficient space. This is to reduce the MOS capacitance by leaving the distance between the wiring portion and the silicon surface as thick as possible. Also, the polysilicon film 1
Since 1 has conductivity, the emitter region 6 and the electrode film 12 via the polysilicon film 11 on the central hole 9 can conduct electricity. This step corresponds to the second photoresist film pattern forming step and the second etching step described in claim 1. Next, Fig. 1
As shown in (j), the polysilicon film 11 and the electrode film 12 are used as an etching mask for the silicon oxide film 4, and the silicon oxide film 4 other than the portion where the polysilicon film 11 and the electrode film 12 remain is etched. At this time, by controlling the etching amount to about 3000 Å, the silicon surface is exposed only at the holes 9 on both sides, and the silicon oxide film 4 is left in the periphery thereof at about 3000 Å. The polysilicon film 11 and the electrode film 12 are not removed during the etching of the silicon oxide film 4. This step corresponds to the third etching step described in claim 1. Then, as shown in FIG. 1 (k), electrodes 13 are formed in the holes 9 on both sides by a lift-off method to complete the high frequency transistor.
The electrode 13 is formed by vacuum-depositing aluminum on the photoresist 10 formed by the second photoresist film pattern forming process while leaving the photoresist 10 left, and then removing the photoresist 10. At this time, the formation of the electrode 13 by the lift-off method is performed by the photoresist 10
Since a step is formed at the break, a gap is surely formed with the electrode film 12 of the central hole 9 which is sufficiently side-etched.
The electrode 13 formed by this lift-off method becomes the base electrode.
The steps shown in FIGS. 1 (j) and 1 (k) correspond to the lift-off electrode forming step described in claim 1.

In the method of manufacturing the high-frequency transistor of this embodiment configured as described above, the central hole 9 serves both as the emitter forming hole and the contact hole for forming the emitter electrode, and the contact hole for forming the base electrode is on both sides. Since the holes 9 are simultaneously formed with one photomask, it is not necessary to set a mask margin, and the polysilicon film 11 can prevent side etching of the central hole 9. Can be made narrower than the stripe width S ₂ of the emitter region 6 in the case of the method of manufacturing the high frequency transistor of the wash emitter type,
Further, it is possible to reduce the base resistance r _o because it can reduce the length of the base contact holes and emitter contact holes. Further, since the position of the base electrode by misalignment of the mask alignment is not to become imbalanced with respect to the emitter region 6, it is possible to prevent the base resistance r _o per unit area increases. Further, since the electrodes are formed by the lift-off method, the base and the emitter electrodes are surely insulated from each other.
It is possible to further reduce the distance between the two, and it is possible to further reduce the collector capacitance C _o and the base resistance r _o per unit area. Therefore, the F. M. An expression that represents In F., the stripe width S of the emitter region 6 can be further narrowed and the collector capacitance C _o and the base resistance r _o per unit can be made smaller. M. It is possible to further increase the value of and improve the high frequency characteristics. Further, in this method of manufacturing a high-frequency transistor, the mask alignment process such as formation of the emitter electrode and formation of the base contact hole is omitted by one mask, and the accuracy is further eased. Labor saving and high efficiency of the manufacturing process can be achieved. Further, when the electrode film 12 is formed in the central hole 9, since vapor deposition is performed through the polysilicon film 11, aluminum of the electrode material penetrates the emitter region 6 and reaches the base region 3 due to a spike phenomenon. There is no fear of short-circuiting between the base and the emitter, and it is possible to prevent a reduction in product yield.

[Brief description of drawings]

1 (a) to 1 (k) are cross-sectional views of a silicon wafer in respective steps in a method of manufacturing a high frequency transistor according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are respectively, FIG. 2 (e) is a cross-sectional view of the silicon wafer in each step of the general transistor manufacturing method, and FIG. 2 (e) shows the silicon wafer when the mask alignment in the step of FIG. 2 (d) in the same transistor manufacturing method is misaligned. Sectional view, Figure 3 (a) ~ (d)
FIG. 3 (e) is a cross-sectional view of a silicon wafer in each step in a conventional method of manufacturing a high frequency transistor.
FIG. 3 is a diagram showing a method of manufacturing the same high frequency transistor.
FIG. 9 is a cross-sectional view of the silicon wafer when the mask alignment is misaligned in the step (d). 1 ... Silicon wafer (semiconductor substrate), 4 ... Silicon oxide film (oxide film), 6 ... Emitter region (diffusion layer), 9 ... Hole, 10 ... Photoresist, 11 ... Polysilicon film, 12 …… Electrode film, 13 …… Electrode.

Claims (1)

[Claims] 1. A hole forming step of forming a plurality of holes in an oxide film on a semiconductor substrate, an oxide film forming step of forming a thin oxide film on the semiconductor substrate, and a photoresist film covering the semiconductor substrate. A first photoresist film pattern forming step of opening a photoresist film above a part of the holes opened in the oxide film; and a first oxide film removing step in which the thin oxide film in the hole portion opened in the photoresist film is removed. Etching process, after removing the photoresist film, forming a polysilicon film on this semiconductor substrate, forming a polysilicon film, and diffusing into the semiconductor substrate under the hole where the thin oxide film was removed from the holes opened in the oxide film. An impurity diffusion step of forming a layer, an electrode film forming step of forming an electrode film on the semiconductor substrate, and a photoresist film on the semiconductor substrate. A second photoresist film pattern forming step of opening a photoresist film above a hole other than the hole for covering and forming a diffusion layer below, and removing the electrode film and the polysilicon film below the opening of the photoresist film A second etching step, and the oxide film is etched using the electrode film and the polysilicon film remaining in the second etching step as an etching mask,
A third etching step of removing a thin oxide film in a hole portion other than the hole in which a diffusion layer is formed below, and a photoresist formed in a second photoresist film pattern forming step after depositing an electrode material on the semiconductor substrate. And a lift-off electrode forming step of forming an electrode in the hole portion where the thin oxide film is removed in the third etching step by removing the film.