JPS62150873A - Semiconductor device - Google Patents

Abstract

PURPOSE:To accurately form an element such as the monolithic resistor of a semiconductor integrated circuit device in a high density by shaping the profile shape of a diffused layer by using etched grooves. CONSTITUTION:A semiconductor substrate that an n<+> type buried layer 2 and an n<-> type epitaxial layer 3 are formed is used for a p<-> type silicon semiconductor substrate 1, and a plurality of monolithic resistors R by p-type diffused layers 4 are aligned in parallel on the layer 3 of the substrate. The resistors R have resistive elements formed of the layers 4 in a plane profile shape using etched grooves 5. Thus, the resistors R can be accurately formed in a high density without difficulty in the process.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device technology and a technology that is particularly effective when applied to a semiconductor integrated circuit device in which a large number of elements are integrated at high density using a diffusion layer. The present invention relates to a technique that is effective for use in a semiconductor integrated circuit device in which a monolithic resistor is formed using a diffusion layer, for example.

[Background technology]

In semiconductor devices, particularly semiconductor integrated circuit devices, many of the elements formed therein are formed by diffusion layers.

Elements formed by this diffusion layer include not only active elements such as bipolar transistors and IIL (Integrated Injection Logic), but also passive elements such as so-called monolithic resistors. For example, the monolithic resistor described in "Integrated Circuit Engineering (1)" published by Corona Co., Ltd., co-authored by Hisayoshi Yanai and Minoru Nagata, first published on April 5, 1970, pages 121-130, is a monolithic resistor, along with bipolar transistors, etc. It is important as an element formed within an integrated circuit device.

FIGS. 1(a) and 1(b) show the structure of the monolithic resistor R mentioned above. FIG. 4(a) shows a cross-sectional state, and FIG. 2(b) shows a planar layout state of a part thereof.

The monolithic resistor R shown in (a) and (b) of FIG. It is formed by partially selectively diffusing a p-diffusion layer 4 into the epitaxial layer 3 and further providing electrodes 7 at both ends of this diffusion layer 40. Note that 6 indicates a surface oxide film.

The resistance value of the monolithic resistor R shown in the figure depends on the dimensions (W and L) of its planar contour shape as well as its diffusion concentration and depth. Therefore, this kind of monolithic resistance R
In order to improve the precision of the resistor, it is necessary to control the concentration and diffusion depth of the diffusion layer 4, which serves as a resistor, as well as the planar contour shape of the diffusion layer 4 with high precision. Furthermore, in order to form a plurality of monolithic resistors R in a high-density integrated manner on a semiconductor integrated circuit device, it is necessary to make the arrangement interval as small as possible. must be controlled with high precision.

However, since the diffusion layer 4 spreads and diffuses not only in the depth direction but also in the lateral direction, even if processes such as photomasking and etching are performed with high precision, it is difficult to define the planar contour shape with high precision and good reproducibility. was extremely difficult. The inventor of the present invention has clarified the problem that this is a major obstacle in improving the precision and formation density of elements such as this type of monolithic resistor R or bipolar transistor.

[Purpose of the invention]

The purpose of this invention is to make it possible to define the contour shape of a diffusion layer for forming elements such as resistors and bipolar transistors with high precision without making the process difficult. The object of the present invention is to provide semiconductor technology that makes it possible to form elements with high precision and high density.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

In other words, by using etching grooves to shape the outline of the diffusion layer that forms the main part or part of devices such as monolithic resistors and bipolar transistors, devices such as resistors and bipolar transistors can be fabricated without complicating the process. It is possible to define the contour shape of the diffusion layer for forming the diffusion layer with high precision, thereby achieving the purpose of making it possible to form elements such as monolithic resistors with high precision and high density. be.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIGS. 1(a) and 1(b) show an embodiment of a main part of a semiconductor integrated circuit device to which the technology according to the present invention is applied. FIG. 4(a) shows a cross-sectional state, and FIG. 2(b) shows a planar layout state of a part thereof. - The semiconductor integrated circuit device partially shown in the same figure has a p-type silicon semiconductor substrate l and an n
A semiconductor substrate on which a medium-sized buried layer 2 and an n-type epitaxial layer 3 are formed is used, and a plurality of monolithic resistors R made of p-diffused diffusion layers 4 are formed in line in the n-type epitaxial layer 3 of this substrate. In this monolithic resistor R, the planar outline of the p-diffusion layer 4 forming the resistor is shaped by the etching groove 5.

The etching groove 5 is formed by reactive sputter etching or electron beam lithography, and the depth hl of the groove 5 is set to be larger than the depth h2 of the p-diffusion layer 4 (hl>h2). From this K, the periphery of the p-diffusion layer 4 is shaved off, and the dimensions (W and L) of its planar contour shape and the spacing between adjacent diffusion layers 4 are determined.

Furthermore, between two adjacent p-diffusion layers 4 separated from each other by an etching groove 5, the substantial distance between them is the same as the lower part of the groove 5, as shown by the symbol d in FIG. is extended by bypassing the bottom. Thereby, separation between adjacent resistors R can be reliably achieved even though the interval pitch D between them is narrowed.

Note that 6 indicates a surface oxide film, and 7 indicates an electrode made of aluminum or the like.

In the monolithic resistor R having the above structure, the contour shape of the p-diffusion layer 4 constituting the resistor is not affected by the lateral spread of the diffusion layer, and the etched groove 5
The formation pattern is precisely defined. This makes it possible to form the resistor R with high precision and high density without making the process difficult.

FIGS. 2(a), 2(b), and 2(c) show a manufacturing method for forming the monolithic resistor R in the order of its main process steps.

First, as shown in FIG. 5A, a semiconductor substrate is used in which an n-type buried layer 2 and an n-type epitaxial layer 3 are formed on a p-type silicon semiconductor substrate 1, and the n-type epitaxial layer 3 of this substrate is The n-type diffusion layer 4 is selectively diffused with rough precision.

Next, as shown in FIG. 5(b), the etched grooves 5 are etched by reactive slat etching or electron beam lithography.
form. As a result, the n-type diffusion layer 4 is divided into a plurality of parts while shaping into a predetermined contour shape and arrangement interval. Note that 8 indicates a mask for forming the etching grooves 5 in a predetermined pattern.

After this, as shown in FIG. 1(c), the surface oxide film 6 is re-formed, and an electrode 7 made of aluminum or the like is formed to form a monolithic resistor R as shown in FIGS. 1(a) and 1(b). get.

FIGS. 3(a), 3(b), and 3(c) show another embodiment of the present invention.

Figures (a), (b), and (c) show a manufacturing method for forming an npn bipolar transistor Tr in the order of its main process steps. To show only its characteristic points, here, the contour shape of the p-type base diffusion layer 4 of the npn bipolar transistor Tr is shaped by the etching groove 5.

In the same figure (, 9 is an n medium-sized emitter diffusion layer, 10 is an n medium-sized collector current collection diffusion layer, and 11 is a p-type isolation diffusion layer. In addition, C is a collector, B is a pace, and E is an emitter. show.

FIG. 4 shows yet another embodiment of the invention.

In the embodiment shown in the figure, IIL (Integrated)
A p-type base diffusion layer 4 (injection logic) is separated and bordered by etching grooves 5 formed at the beveled edges. This makes it possible to narrow the arrangement pitch D between each IIL and increase the integration density.

In the figure, INJ is a p-type injector region, and B is an n-type injector region.
The space formed by the type diffusion layer 4, C1 and C2 respectively indicate the collector formed from the n+ type diffused layer.

〔effect〕

(11) By using etching grooves to shape the outline of the diffusion layer that forms the main part or part of devices such as monolithic resistors and bipolar transistors, devices such as resistors and bipolar transistors can be fabricated without complicating the process. It becomes possible to define the contour shape of the diffusion layer for forming with high precision, and this has the effect that, for example, elements such as monolithic resistors can be formed with high precision and high density. .

The invention made by the present inventor has been specifically explained based on examples.It goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, the diffusion layer 4
may be an n-type diffusion layer formed in a p-type semiconductor region.

[Application field]

The above description has been made of the case where the invention made by the present inventor is applied to the technology of semiconductor devices in which monolithic resistors, bipolar transistors, IILs, etc. are formed, which is the background application field, but the present invention is not limited to this. Rather, it can also be applied to, for example, semiconductor device technology in which a monolithic capacitor using a diffusion layer or an MO8 element is formed. It is applicable to conditions where an element is formed by a diffusion layer that is at least partially selectively diffused.

[Brief explanation of drawings]

1(a) and 1(b) are diagrams showing an embodiment of the semiconductor device according to the present invention, and FIG. A diagram showing the stages in order, Figure 3 (
a), (b), and (c) are diagrams sequentially showing the main steps of the manufacturing process of a semiconductor device according to another embodiment of the present invention; FIG. 4 is a diagram showing still another embodiment of the present invention; FIGS. 5(a) and 5(b) are diagrams showing the structure of a semiconductor device that has been studied prior to the present invention. l...p-type silicon conductor substrate, 2...n medium-sized buried layer, 3...n-type epitaxial layer, 4...p-type diffusion layer for forming any element of resistor tx, 5...Etched groove, R...Resistance. /Katsuo Ogawa, Patent Attorney, J., No.
1 Figure (/,) Figure 2 Figure 3 Figure I construction Figure 5 ((L)

Claims (1)

[Claims] 1. A semiconductor device in which an element is formed by a diffusion layer partially selectively diffused into a semiconductor substrate, wherein the planar outline of the diffusion layer is shaped by an etching groove. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the element is a diffused resistor.