JPS5858761A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5858761A
JPS5858761A JP15840781A JP15840781A JPS5858761A JP S5858761 A JPS5858761 A JP S5858761A JP 15840781 A JP15840781 A JP 15840781A JP 15840781 A JP15840781 A JP 15840781A JP S5858761 A JPS5858761 A JP S5858761A
Authority
JP
Japan
Prior art keywords
collector
base
emitters
regions
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15840781A
Other languages
Japanese (ja)
Inventor
Takaaki Nakada
孝明 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15840781A priority Critical patent/JPS5858761A/en
Publication of JPS5858761A publication Critical patent/JPS5858761A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To equalize emitter currents, and to improve a high-frequency characteristic by alternately arranging region sections, which contain one or two emitters divided and bases with base contact windows at both sides of the emitters, and collector contact windows in a large number. CONSTITUTION:An N<+> buried layer 7 is formed to a high-resistivity P<-> substrate 6, and a collector layer 8 is shaped onto the layer 7. A plurality of the base regions 9 using the two emitters 1 divided with the base contact windows 2 at both sides as units are formed to the collector layer 8. Collector extracting regions 12 are shaped at both sides of the regions 9, and an electrode 11 is formed to the regions 12 through the collector contact windows 5. Accordingly, base resistance is reduced while realizing a large emitter area by a plurality of the emitters 1, distances up to the windows 5 are equalized by the emitters 1 divided, collector resistance is made uiform, and equal currents are flowed.

Description

【発明の詳細な説明】 本発明は特にモノリシック集積回路を構成するバイポー
ラトランジスタの構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates in particular to the structure of bipolar transistors forming monolithic integrated circuits.

高周波モノリシック集積回路の田力段に使用するバイポ
ーラトランジスタは、コレクタ電流を多く流す必要上工
建ツタ面積を大きく設計されるが、その場合ベース抵抗
の増加を来し高周波特性の劣化を招く。そのため、従来
は第1図a及びそのA−N断面である第1図すに示す様
に、デスクy −ト高周波バイポーラトランジスタで用
いられていた、例えばエンツタを複数のストライプ匿エ
ミッタ20に分割し、それぞれのエンツタ1の両側よp
ベースコンタクト窓2t−設けてベース電極41ft:
接続するような方法でベース抵抗の減少を計っていた。
Bipolar transistors used in the power stages of high-frequency monolithic integrated circuits are designed with a large construction area to allow a large collector current to flow, but in this case, the base resistance increases and the high-frequency characteristics deteriorate. Therefore, conventionally, as shown in FIG. , both sides of each entreta 1 p
Base contact window 2t - base electrode 41ft:
I was trying to reduce the base resistance by connecting it.

tた、コレクタは素子の表面よシ引出し電極で接続する
必要上、第1図すの様に埋込層7およびコレクタコンタ
クト窓5を介してコレクタ引出し電極10に接続してい
た。同、3はエミッタ電極であり、6はP−基板である
In addition, since the collector needs to be connected to the surface of the element through the lead electrode, it is connected to the collector lead electrode 10 through the buried layer 7 and the collector contact window 5 as shown in FIG. 3 is an emitter electrode, and 6 is a P-substrate.

しかしこの場合、それぞれの分割された工電ツタ20間
でコレクタ外窓5への距離が異なる九め、コレクタ抵抗
の差が生じて、それぞれの工(ツタ電流が不均等となる
ことより、十分な高周波特性を得ることが困難であり几
However, in this case, the distances to the collector outer window 5 are different between the divided power vines 20, and the collector resistances are different. It is difficult to obtain accurate high frequency characteristics.

本発明は、上記欠点を改善して良好な高周波特性のトラ
ンジスタを有する半導体装置を提供するものである。
The present invention aims to improve the above-mentioned drawbacks and provide a semiconductor device having a transistor with good high frequency characteristics.

本発明による半導体装置は、1本又は2本の分割され九
工(ツタおよびその両側にベースコンタクト窓會有する
ベースを含んでなる領域部とコレクタコンタクト窓とを
交互に多数配置したものであり、かかる構造によ)ベー
ス抵抗を減少し、かつ分割された各エンツタよシコレク
タコンタクト窓までの距離を等しくしてそれぞれのエミ
ッタ電流を均一にし、良好な高周波特性が得られる。
The semiconductor device according to the present invention is one in which a large number of region portions including one or two divided vines and a base having base contact windows on both sides thereof and collector contact windows are arranged alternately, With this structure, the base resistance can be reduced (and the distances from the divided entrants to the collector contact windows can be made equal, so that the respective emitter currents can be made uniform, and good high frequency characteristics can be obtained).

以下本発明の実施例を図によってより詳細に説明するに
NPN型トランジスタを例とする。
Hereinafter, embodiments of the present invention will be explained in more detail with reference to the drawings, taking an NPN type transistor as an example.

本発明の一実施例を第2図a及びその人−N断面を第2
図すに示す様に、従来と同様高比抵抗P”サブストレー
ト6にN+埋込層7t−形成してその上にN型コレクタ
層8を形成する。このコレクタ層8に、両側にベースコ
ンタクト窓2を有する分割されたエミッタ1t−2本為
ニットとし九複数のベース領域9t−従来同様にイオン
注入または熱拡散法等で形成する。i九ベース領域9の
両側にはコレクタ引出し領域12t−設け、これにコレ
クタコンタクト窓5を介してコレクタ引出し電極11全
形成する。
One embodiment of the present invention is shown in Fig. 2a, and the person-N cross section is shown in Fig. 2a.
As shown in the figure, an N+ buried layer 7t- is formed on a high specific resistance P'' substrate 6 as in the conventional case, and an N type collector layer 8 is formed thereon. Base contacts are formed on both sides of this collector layer 8. A divided emitter 1t having a window 2 is formed by a plurality of base regions 9t by ion implantation or thermal diffusion as in the conventional method.On both sides of the base region 9 are collector lead-out regions 12t. The collector lead electrode 11 is entirely formed thereon via the collector contact window 5.

ま九第2図aのB−ff断面である第2図Cに示す様に
、エミッタ引出し電極3の途中に工電ツタ安定化抵抗層
10t−介するようにして、コレクタ引出し電極11と
の交差をさける。
As shown in FIG. 2C, which is a B-ff cross section of FIG. Avoid.

K2図a、bおよびCに示す様な構造のトランジスタを
構成することで、複数のエンツタ1によシ大きなエンツ
タ面積を実現しつつベース抵抗の低減全針に、それぞれ
の分割され之エミッタ1よりコレクタコンタクト窓5t
での距離を等しくしてコレクタ抵抗を均一にし、それら
の二(ツタlに均等なエミッタ電流を流すことが可能で
あり、大きなコレクタ電流で使用しても高周波特性の優
しタパイボー2トランジスタが実現可能となる。
By configuring a transistor with the structure shown in Figure K2 a, b, and C, it is possible to realize a large emitter area for multiple emitters 1 while reducing the base resistance. Collector contact window 5t
It is possible to make the collector resistance uniform by making the distance between the two transistors equal, and it is possible to flow an equal emitter current to the two transistors, making it possible to create a Tapaibo 2 transistor with gentle high-frequency characteristics even when used with a large collector current. becomes.

また第2図Cに示す様なエイツタ安定化抵抗層10t−
使用しない時は、電極の多層配線によジエンツタ引出し
電極とコレクタ引出し電極の交差をさけることができる
In addition, a stabilizing resistance layer 10t- as shown in FIG.
When not in use, the multi-layer wiring of the electrodes can avoid crossing of the collector lead-out electrodes and the generator lead-out electrodes.

ここではNPN型トランジスタについて説明し2が、P
NP型トランジスタについても同様に本発明が実施可能
なことは言うまでもない、また、エンツタ1は1本でも
よい。
Here, we will explain the NPN type transistor, and 2 is the P
It goes without saying that the present invention can be similarly implemented with respect to NP type transistors, and the number of entrants 1 may be one.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a及びbはそれぞれ従来トランジスタの平面図お
よびその人−N断面図である。第2図a。 bおよびCは、それぞれ本発明の一実施nt示すトラン
ジスタの平面図、A−N断面図およびB−N断面図であ
る。 l・・・・・・工ζツタ、2・・・・・・ベースコンタ
クト窓、3・・・・・・エミッタ引出し電極、4・・・
・・・ベース引出し電極、5・・・・・・コレクタコン
タクト窓、6・・・・・・P−サプストレート、7・・
・・・・N+コレクタ埋込層、8・・・・・・N型コレ
クタ層、9・・・・・・ベース領域、10・・・・・・
工ζツタ安定化抵抗層、11・・・・・・コレクタ引出
し電極、12・・・・・・コレクタ引出し領域。 工〉
FIGS. 1A and 1B are a plan view and a cross-sectional view taken along the line-N of a conventional transistor, respectively. Figure 2a. B and C are a plan view, an AN sectional view, and a BN sectional view, respectively, of a transistor showing one embodiment of the present invention. l...Engine ζ ivy, 2...Base contact window, 3...Emitter extraction electrode, 4...
... Base extraction electrode, 5 ... Collector contact window, 6 ... P-substrate, 7 ...
...N+ collector buried layer, 8...N type collector layer, 9...base region, 10...
Ivy stabilizing resistance layer, 11...Collector extraction electrode, 12...Collector extraction region. Engineering〉

Claims (1)

【特許請求の範囲】[Claims] 複数に分割されたエンツタを有し、その1本又は2本ご
とに応じてベース領域も分割し、複数の前記ベース領域
とコレクタコンタクト窓とが父互に配置されて成るバイ
ポーラトランジスタを有すること全特徴とする半導体装
置。
The bipolar transistor has a plurality of divided entrants, a base region is also divided according to one or two of them, and a plurality of base regions and collector contact windows are mutually arranged. Characteristic semiconductor devices.
JP15840781A 1981-10-05 1981-10-05 Semiconductor device Pending JPS5858761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15840781A JPS5858761A (en) 1981-10-05 1981-10-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15840781A JPS5858761A (en) 1981-10-05 1981-10-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5858761A true JPS5858761A (en) 1983-04-07

Family

ID=15671073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15840781A Pending JPS5858761A (en) 1981-10-05 1981-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5858761A (en)

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