JPS6045033A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent any parasitic effect effectively by a method wherein a separation region between the first and the second island region is grounded. CONSTITUTION:A one conductive type semiconductor substrate 21, an inverse conductive type epitaxial layer 22 deposited on the substrate 21, another one conductive type separation region 22 vertically separating the epitaxial layer 22 into two island regions 23, 24, a vertical type transistor P-N-P transistor 32 provided on the first island region 23 and an adjoining second island region 24 are provided while the separation region 25 between the first island region 23 and the second island region 24 is grounded. A grounded electrode 33 coming into ohmic contact with the separation region 25 and other specified electrodes are simultaneously formed on one end or both ends of the separation region 25 by aluminium evaporation to be connected to grounded potential. Therefore the integration of a semiconductor integrated circuit may be improved by saving any surplus space to prevent parasitic effect since any parasitic thyristor effect may be easily prevented by the grounded electrode 33 only.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor integrated circuit that eliminates thyristor parasitic effects.

(B) Prior art As shown in Figure 1, a conventional semiconductor integrated circuit consists of a P-type semiconductor substrate (1), an N-type epitaxial layer (1) and an epitaxial layer (2) laminated thereon. A P+ type separation region (5) that separates the upper and lower parts of each island region (3) and (4);
Furnace-shaped buried layer (6) provided at the bottom of each island area (3 bars 4)
) and a P+ type collector region (7) a P+ type collector lead-out region (8) an N type base region (9) an N'' type base contact region 0Q and a P type emitter region dll formed in the first island region (3). The run risk (Iz) is composed of a vertical PNP (Iz), and an oval-shaped tunnel resistance region 031 formed in an adjacent second island region (4).

In such a semiconductor integrated circuit, vertical PNP) run risk 02
emitter region (Ill is biased to a high potential and the second
When the island region (4) or the tunnel resistance region (+3) is biased to a low potential, the emitter region (01) base region (9) collector region (7) first island region (3) isolation region (5) and A PNPNPN self-circuit type parasitic thyristor is formed in the second island region (4), and when the parasitic thyristor is turned on, a parasitic current flows as shown by the arrow.

FIG. 2 is an equivalent circuit diagram of a parasitic thyristor.

Tr is the original PNP) run risk formed by the emitter region Qll base region (9) and collector region (7) of the vertical PNP) run risk 02);
is the vertical PNP of space region (9) collector region (7) and first island region (3) NPN) run risk formed of the epitaxial layer outside the run risk a2, and Trl is the collector region ( 7) PNP formed in the above-mentioned outer epitaxial layer and isolation region (5))
Tr4 is a run risk, and Tr4 is an NPN transistor formed by the aforementioned outer epitaxial waste isolation region (5) and second island region (4).

In order to effectively prevent such a parasitic thyristor effect, conventionally the epitaxial layer outside the first island region (3) described above was connected to the power supply voltage. However, this method requires routing power lines, which poses an obstacle in terms of the degree of integration.

PI OBJECTS OF THE INVENTION The present invention has been made in view of the discontinuity, and provides a semiconductor integrated circuit in which parasitic effects can be completely and easily prevented.

2) Structure of the Invention The semiconductor integrated circuit according to the present invention, as shown in FIG.
A separation region (c) of one conductivity type that separates the island into a plurality of island regions (2 Q4) above and below, a first island region (231 vertical PNP), and an adjacent second Island area (2
4), and is constructed by grounding the separation region (c) between the first island region Q□□□ and the second island region Q4).

(e) Example In this example, as shown in FIG. 3, an N-type silicon epitaxial layer (
This epitaxial layer (22) is separated from the top and bottom by PN+ in the P" type separation region (2), and each island region (to) (3
Form 4+. N1 at the bottom of each island area (c) Q4)
A mold embedding layer (c) is provided. The first island region Q includes a P+ type collector region Q7) provided on the buried layer (C) and a P which reaches the collector region (27) from the surface.
+ type collector derivation area (2 (to) and collector area (2)
Also provided is a first vertical PNP transistor G2 surrounded by a base region (+!1), an end of an N' type base contact region, and a P+ type emitter region CI+1.An adjacent second island region Qa The epitaxial layer (the second layer is used as it is as an epitaxial resistor, or the N+ type resistance region 04 is further diffused and used as a tunnel resistor).

The feature of the present invention is that the first island region (c) and the second island region CI
'4) It is possible to ground the separation area (c) in between.

Separation area C! 5) At one end or both ends, a ground electrode (material) in ohmic contact with the isolation region (c) is formed by aluminum vapor deposition at the same time as other desired electrodes, and is connected to the ground potential.

The equivalent circuit of the above structure is shown in FIG.
Tr2, 'l'r3, and Tr4 have the same configuration as in FIG. 2, and the potentials of the collector of Trs and the base of Tr40 are grounded. As a result, the part corresponding to the gate of the parasitic thyristor is grounded and no self-bias is applied, so that the parasitic thyristor effect can be completely prevented.

Note that the ground electrode 01 is connected to the first or second island region (c) (
It is also possible to set up traps to almost completely surround 24+.

According to the present invention, parasitic thyristor effects can be easily prevented by using a grounded electrode system, and the degree of integration of semiconductor integrated circuits can be increased by eliminating extra space for preventing parasitic effects. You can improve. Further, since the ground ML pole can be formed on a conventional isolation region (c) and no additional steps are required for formation, it can be easily applied to current semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a sectional view for explaining a conventional example, FIG. 2 is an equivalent circuit diagram for the conventional example, FIG. 3 is a sectional view for explaining the present invention, and FIG. 4 is an equivalent circuit diagram for the present invention. Explanation of main figure numbers: Qυ is the semiconductor substrate, (2 is the epitaxial layer, (g)
is the first island area, C! 02 is the vertical PNP, the run risk is the second island area, (g) is the separation area, and 02 is the ground electrode. Fig. 1 Fig. 11 Fig. 21 No. 41 < 1

Claims (1)

[Claims] (1) - comprising a semiconductor substrate of a conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate, and a separation region of one conductivity type for separating the epitaxial layer into a plurality of island regions;
In a semiconductor integrated circuit in which a thyristor parasitic effect occurs between a vertical PNP transistor provided in an island region and an adjacent second island region, a separation region between the first island region and the second island region is grounded. A semiconductor integrated circuit characterized by: