JPH0126545B2 - - Google Patents
Info
- Publication number
- JPH0126545B2 JPH0126545B2 JP57125541A JP12554182A JPH0126545B2 JP H0126545 B2 JPH0126545 B2 JP H0126545B2 JP 57125541 A JP57125541 A JP 57125541A JP 12554182 A JP12554182 A JP 12554182A JP H0126545 B2 JPH0126545 B2 JP H0126545B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- collector
- base
- region
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000605 extraction Methods 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明はトランジスタの構造に関するもので、
特に、ベース及びエミツタ、コレクタの引き出し
用電極の構造に特徴を有するマルチトランジスタ
の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a transistor,
In particular, the present invention relates to a multi-transistor structure characterized by the structure of the base, emitter, and collector lead-out electrodes.
単一のエミツタ―ベース―コレクタ構造ではな
く、複数のエミツタ―ベースを形成することによ
つてトランジスタの特性を向上させることが考え
られている。この場合にコレクタ埋込み層のない
構造とするとコレクタ領域の抵抗が大きくなるた
めに、良好な伝達特性を得にくくなる。従来、一
般に用いられるマルチエミツタトランジスタにお
いては、複数の分離したベース拡散領域にそれぞ
れエミツタ拡散領域を形成し、それらのベース拡
散領域の下方にコレクタ埋込み層を形成したもの
が知られている。これによつて電流特性の伸びを
良くすることが考えられている。 It has been considered to improve the characteristics of a transistor by forming a plurality of emitter bases rather than a single emitter base collector structure. In this case, if a structure without a collector buried layer is adopted, the resistance of the collector region increases, making it difficult to obtain good transfer characteristics. Conventionally, a commonly used multi-emitter transistor is known in which an emitter diffusion region is formed in each of a plurality of separate base diffusion regions, and a collector buried layer is formed below the base diffusion regions. It is thought that this will improve the elongation of the current characteristics.
上記のように、埋込み層を用いることのできる
マルチトランジスタにおいては、良好な伝達特性
を得ることが可能となるが、埋込み層の形成が容
易なエピタキシアル構造ではない、誘電体分離構
造、SOS構造のようなトランジスタにおいては埋
込み層の形成が困難となり、満足な特性を得るこ
とが難しくなる。 As mentioned above, it is possible to obtain good transfer characteristics in a multi-transistor that can use a buried layer. In such transistors, it is difficult to form a buried layer, making it difficult to obtain satisfactory characteristics.
本発明は、上記のような問題を解決して、埋込
み層のない構造においてマルチトランジスタの特
性を向上させることを目的とするものである。特
に、薄膜トランジスタとして、誘電体分離、SOS
構造に適したマルチトランジスタを得ることを目
的とする。 The present invention aims to solve the above problems and improve the characteristics of a multi-transistor in a structure without a buried layer. In particular, as thin film transistors, dielectric isolation, SOS
The aim is to obtain a multi-transistor structure suitable for the structure.
埋込み層を用いない誘電体分離によるマルチト
ランジスタとして、ベース領域の周囲に高濃度層
を形成してこれにコレクタ引出し用電極を接続す
るものが提案されている。本発明は、このような
構造のマルチトランジスタの構造の改良に関する
ものである。 As a multi-transistor using dielectric isolation without using a buried layer, one has been proposed in which a highly doped layer is formed around a base region and a collector lead-out electrode is connected to this layer. The present invention relates to an improvement in the structure of a multi-transistor having such a structure.
本発明によるマルチトランジスタは、複数のベ
ース拡散領域内にそれぞれエミツタ拡散領域を形
成するとともに、ベース拡散領域の周囲に高濃度
に不純物がドープされたコレクタ引出し用の拡散
層を形成した構造で、ベース引出し用電極、コレ
クタ引出し用電極、エミツタ引出し用電極に次の
ような特徴を有するものである。第一に、ベース
引出し用電極を引き出す方向と、コレクタ引出し
用電極及びエミツタ引出し用電極を引き出す方向
とが逆方向となつている点である。第二に、エミ
ツタ引出し用電極は拡散抵抗領域の一端に接続さ
れ、他端からまた引き出されるとともに、この拡
散抵抗領域とコレクタ引出し用電極とが絶縁層を
介して交差している点である。 The multi-transistor according to the present invention has a structure in which an emitter diffusion region is formed in each of a plurality of base diffusion regions, and a collector extraction diffusion layer doped with impurities at a high concentration is formed around the base diffusion region. The extraction electrode, the collector extraction electrode, and the emitter extraction electrode have the following characteristics. First, the direction in which the base extraction electrode is drawn out is opposite to the direction in which the collector extraction electrode and the emitter extraction electrode are drawn out. Second, the emitter lead-out electrode is connected to one end of the diffused resistance region and drawn out from the other end, and the diffused resistance region and the collector lead-out electrode intersect with each other via an insulating layer.
以下、図面に従つて、本発明の実施例につき説
明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明によるマルチトランジスタの
一例を示す平面図である。ある導電型のシリコン
基板に複数の反対導電型の拡散領域が形成されこ
れがベース領域１１となる。したがつて、このベ
ース領域の周囲のある導電型の基板はコレクタ領
域１２となる。ベース領域１１の中にある導電型
の不純物を拡散した領域が形成されてエミツタ領
域１３となる。ベース領域１１を取り囲むコレク
タ領域には、ある導電型の不純物が高濃度にドー
プされたコレクタ引出し用拡散層１４が形成され
ている。ベース領域１１はそれぞれベース引出し
用電極１５にオーム性接続されて引き出される。
同様に、エミツタ領域１３はエミツタ引出し用電
極１６に、コレクタ引出し用拡散層１４はコレク
タ引出し用電極１７に接続されている。 FIG. 1 is a plan view showing an example of a multi-transistor according to the present invention. A plurality of diffusion regions of the opposite conductivity type are formed in a silicon substrate of a certain conductivity type, and these become the base region 11 . Therefore, a certain conductivity type substrate around this base region becomes the collector region 12. A region in which conductive type impurities are diffused in the base region 11 is formed and becomes the emitter region 13. A collector region surrounding the base region 11 is formed with a collector lead-out diffusion layer 14 doped with impurities of a certain conductivity type at a high concentration. The base regions 11 are each ohmically connected to a base extraction electrode 15 and extracted.
Similarly, the emitter region 13 is connected to the emitter lead-out electrode 16, and the collector lead-out diffusion layer 14 is connected to the collector lead-out electrode 17.
第２図は、第１図に示したマルチトランジスタ
のＸ―X′断面図である。これで明らかなように、
ある、半導体基板に反対導電型の不純物がドープ
された拡散領域を形成してこれをベース領域１１
とし、次にベース領域内にある導電型の不純物が
ドープされてエミツタ領域１３が拡散される。更
にある導電型の不純物が高濃度にドープされたコ
レクタ引出し用拡散層１４が形成されて、同じ基
板の表面部分に複数のエミツタ、ベース、及びコ
レクタを有するトランジスタが形成される。複数
のエミツタ、ベース、コレクタはそれぞれ、エミ
ツタ引出し用電極１６、ベース引出し用電極１
５、コレクタ引出し用電極１７に接続されて同じ
信号伝送路に接続されている。 FIG. 2 is a sectional view taken along line XX' of the multi-transistor shown in FIG. As is clear from this,
A diffusion region doped with an impurity of an opposite conductivity type is formed in a semiconductor substrate, and this is used as a base region 11.
Then, the base region is doped with a conductivity type impurity and the emitter region 13 is diffused. Furthermore, a collector extraction diffusion layer 14 doped with a certain conductivity type impurity at a high concentration is formed, and a transistor having a plurality of emitters, bases, and collectors is formed on the same substrate surface portion. A plurality of emitters, bases, and collectors each have an emitter extraction electrode 16 and a base extraction electrode 1.
5. Connected to the collector extraction electrode 17 and connected to the same signal transmission path.
第１図に示されているように、複数本の引出し
用電極はそれぞれ同一領域に接続されているもの
同士が同じ方向に接続されており、コレクタ領域
の外側において接続されている。すなわち、ベー
ス引出し用電極１５は絶縁層上を図の左側に引き
出されて接続されており、同様にコレクタ引出し
用電極１７は図の右側に引き出されて接続されて
いる。エミツタ引出し用電極１６は、ベース引出
し用電極１５と反対の方向、すなわちコレクタ引
出し用電極１７と同じ方向に引き出される。 As shown in FIG. 1, the plurality of lead-out electrodes are connected to the same area and connected in the same direction, and are connected outside the collector area. That is, the base lead-out electrode 15 is drawn out and connected to the left side of the figure on the insulating layer, and the collector lead-out electrode 17 is similarly drawn out and connected to the right side of the figure. The emitter extraction electrode 16 is extracted in the opposite direction to the base extraction electrode 15, that is, in the same direction as the collector extraction electrode 17.
上記のように、複数のエミツタ引出し用電極１
６と複数のコレクタ引出し用電極１７とが同じ方
向に引き出される場合には、電極を交差させなけ
ればならなくなる。そこで、本発明によるマルチ
トランジスタにおいては、第１図に示すように、
拡散抵抗領域１８を形成してこれにエミツタ引出
し用電極１６を接続する。すなわち、第３図に示
すように、基板と反対導電型の不純物をドープし
た拡散抵抗領域１８が形成されて、その一端にエ
ミツタ引出し用電極１６が接続され、他端には信
号を取り出すための電極が形成される。拡散抵抗
領域１８の表面にはSiO2などの絶縁層１９が形
成され、その上にコレクタ引出し用電極１７が配
線される。 As mentioned above, a plurality of emitter extraction electrodes 1
6 and a plurality of collector extraction electrodes 17 are extracted in the same direction, the electrodes must be crossed. Therefore, in the multi-transistor according to the present invention, as shown in FIG.
A diffused resistance region 18 is formed and an emitter lead-out electrode 16 is connected thereto. That is, as shown in FIG. 3, a diffused resistance region 18 doped with an impurity of conductivity type opposite to that of the substrate is formed, and an emitter extraction electrode 16 is connected to one end of the diffusion resistance region 18, and a signal extraction electrode is connected to the other end. Electrodes are formed. An insulating layer 19 made of SiO 2 or the like is formed on the surface of the diffused resistance region 18, and a collector lead-out electrode 17 is wired thereon.
本発明によるマルチトランジスタの等価回路を
第４図に示す。信号の流れはベースＢからエミツ
タＥという方向となる。すなわち、それぞれのト
ランジスタのベースに印加される信号に従つてエ
ミツタから信号が得られるようになるもので、エ
ミツタには抵抗が接続されたことになる。 FIG. 4 shows an equivalent circuit of a multi-transistor according to the present invention. The signal flow is from base B to emitter E. That is, a signal is obtained from the emitter in accordance with the signal applied to the base of each transistor, and a resistor is connected to the emitter.
本発明によるマルチトランジスタにおいては、
信号の伝播遅延を考慮して、ベースとエミツタを
逆方向に引き出しており、しかも、コレクタとエ
ミツタを前記のような手段によつて交差させてい
る。これによつて電流集中を抑圧できるという効
果だけでなく、直流的なベース・エミツタ間の電
圧の分配が良好となるとともに、交流的な信号の
伝播遅延が揃うために高周波特性の伸びが生じ
る。したがつて、第５図に示すように、応答特性
も入力信号ａに対して出力信号ｂが得られるよう
になる。従来の出力信号ｃに比較して忠実にパル
ス波形を再現できるようになつている。このよう
な特性は、従来の単一のコレクタを用いた構造の
トランジスタでは得ることができない。また、エ
ミツタを拡散抵抗層に接続して交差しているの
で、帰還効果によつて電流分配の均一化が行なわ
れる利点もある。なお拡散抵抗領域１８はアルミ
等の配線層を用いた多層配線によつて構成しても
よいことは当然である。 In the multi-transistor according to the present invention,
In consideration of signal propagation delay, the base and emitter are drawn out in opposite directions, and the collector and emitter are crossed by the above-mentioned means. This not only has the effect of suppressing current concentration, but also improves DC base-emitter voltage distribution and equalizes the propagation delays of AC signals, resulting in an increase in high-frequency characteristics. Therefore, as shown in FIG. 5, the response characteristic is such that an output signal b is obtained for an input signal a. Compared to the conventional output signal c, the pulse waveform can be reproduced more faithfully. Such characteristics cannot be obtained with a conventional transistor having a structure using a single collector. Furthermore, since the emitters are connected to and intersect with the diffused resistance layer, there is an advantage that the current distribution is made uniform due to the feedback effect. It goes without saying that the diffused resistance region 18 may be constructed by multilayer wiring using wiring layers made of aluminum or the like.
第１図は本発明によるマルチトランジスタの一
例の平面図、第２図はその側面断面図、第３図は
同じく部分正面断面図であり、第４図は本発明に
よるマルチトランジスタの等価回路図、第５図は
その応答特性図を示す。
１１…ベース領域、１２…コレクタ領域、１３
…エミツタ領域、１４…コレクタ引出し用拡散
層、１５…ベース引出し用電極、１６…エミツタ
引出し用電極、１７…コレクタ引出し用電極、１
８…拡散抵抗領域、１９…絶縁層。
FIG. 1 is a plan view of an example of a multi-transistor according to the present invention, FIG. 2 is a side sectional view thereof, FIG. 3 is a partial front sectional view thereof, and FIG. 4 is an equivalent circuit diagram of the multi-transistor according to the present invention. FIG. 5 shows its response characteristic diagram. 11...Base area, 12...Collector area, 13
... Emitter region, 14... Diffusion layer for collector extraction, 15... Base extraction electrode, 16... Emitter extraction electrode, 17... Collector extraction electrode, 1
8... Diffused resistance region, 19... Insulating layer.
Claims (1)
拡散領域が形成され、該ベース拡散領域の周囲に
コレクタ引き出し用高濃度拡散領域を形成したマ
ルチトランジスタにおいて、複数のエミツタ及び
コレクタの電極の引き出し方向とベースの電極の
引き出し方向が逆方向となるように電極が形成さ
れ、かつ、エミツタ引き出し電極は抵抗領域を介
して引き出され、該抵抗領域とコレクタ引き出し
電極が絶縁層を介して交差したことを特徴とする
マルチトランジスタ。1. In a multi-transistor in which an emitter diffusion region is formed in each of a plurality of base diffusion regions, and a high-concentration diffusion region for extracting a collector is formed around the base diffusion region, the extraction direction of the plurality of emitter and collector electrodes and the base The electrodes are formed so that the electrodes are drawn out in opposite directions, the emitter lead-out electrode is led out through a resistance region, and the resistance region and the collector lead-out electrode intersect with each other via an insulating layer. Multi-transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57125541A JPS5916367A (en) | 1982-07-19 | 1982-07-19 | Multi-transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57125541A JPS5916367A (en) | 1982-07-19 | 1982-07-19 | Multi-transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5916367A JPS5916367A (en) | 1984-01-27 |
| JPH0126545B2 true JPH0126545B2 (en) | 1989-05-24 |
Family
ID=14912745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57125541A Granted JPS5916367A (en) | 1982-07-19 | 1982-07-19 | Multi-transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5916367A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5307377B2 (en) * | 2007-10-05 | 2013-10-02 | 新日本無線株式会社 | Power amplifier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5162979A (en) * | 1974-11-29 | 1976-05-31 | Mitsubishi Electric Corp | |
| JPS5255476A (en) * | 1975-10-31 | 1977-05-06 | Fujitsu Ltd | Semiconductor device |
-
1982
- 1982-07-19 JP JP57125541A patent/JPS5916367A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5162979A (en) * | 1974-11-29 | 1976-05-31 | Mitsubishi Electric Corp | |
| JPS5255476A (en) * | 1975-10-31 | 1977-05-06 | Fujitsu Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5916367A (en) | 1984-01-27 |
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