JPH0481342B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar type semiconductor integrated circuit in which circuit elements such as PNP transistors and NPN transistors are formed on one semiconductor substrate, and in particular, the present invention relates to a bipolar semiconductor integrated circuit in which circuit components such as PNP transistors and NPN transistors are formed on a single semiconductor substrate.
This invention relates to an improvement in a crossover interposed in a connection with a collector of a transistor.

Generally, NPN transistors are mainly used in bipolar integrated circuits, but there are cases in which it is advantageous to combine PNP transistors, such as in constant current power supply circuits, due to the circuit configuration. An example of a conventional bipolar integrated circuit of this type is shown and explained in FIG. 1. In FIG. 1, 1 is a P-type silicon single crystal substrate (hereinafter referred to as a P-type substrate);
2, 3 and 4 are N ⁺ buried layers with high N type impurity concentration formed on the P type substrate 1, 5, 6 and 7 are N type epitaxial layers, 8 is a P type separation wall, 9,
10, 11 and 12 are P-type diffusion layers formed in each of the epitaxial layers, and 13, 14, 15 and 16 are N-type diffusion layers with a high N-type impurity concentration also formed in each of the epitaxial layers. , 17
is an insulating film such as SiO ₂ or Si ₃ N ₄ , and 18 and 19 are wiring conductors such as aluminum. Also, 21
is a lateral PNP transistor with the P-type diffusion layer 10 as the emitter, the N-type diffusion layer 13, the N-type epitaxial layer 5 and the N ⁺ buried layer 2 as the base, and the P-type diffusion layer 9 as the collector, 22 is a crossover, 23 is an emitter of the N type diffusion layer 16, and P
This is a vertical NPN transistor having the N type diffusion layer 12 as the base and the N ⁺ diffusion layer 15, the N type epitaxial layer 7, and the N ⁺ buried layer 4 as the collector.

In an integrated circuit having such a configuration, the base of the PNP transistor 21 and the NPN transistor 2
When connecting the collectors of transistors 3 and 3, if there is a wiring conductor 19 between the base and collector of these transistors and it is impossible to connect them directly with a wiring conductor, P
This P-type diffusion layer 1 is connected via a P-type diffusion layer 11.
A crossover 22 is formed in which 1 is a lower layer wiring and the wiring conductor 19 is an upper layer wiring. Further, the N type diffusion layer 14 and the N ⁺ buried layer 3 are the N type epitaxial layer 6.
The potential is always biased higher than the potential of the separated type 8 and the P-type diffusion layer 11.

However, in such a conventional bipolar integrated circuit, the P-type diffusion layer 11, which is the lower wiring of the crossover 22, is formed in the same process as the P-type diffusion layers of the horizontal PNP transistor 21 and the vertical NPN transistor 23. Therefore, the layer resistance value is relatively large, 60 to 300 Ω/□, and if the resistance of several tens of Ω cannot be ignored in the lower layer wiring of the crossover 22, it cannot be used.
Since the NPN transistor 23 must be surrounded by another separation wall 8, there are drawbacks such as the need for an extra base.

In view of the above points, this invention was made to eliminate such conventional drawbacks, and its purpose is to:
It is an object of the present invention to provide a bipolar integrated circuit in which the area of a crossover interposed between the base of a PNP transistor and the collector of an NPN transistor is reduced, and the resistance value of the underlying wiring is reduced.

In order to achieve such an object, the present invention provides a first N ⁺ type diffusion layer 20 formed on the N ⁺ type buried layers 2, 3, and 4 formed on the P type semiconductor substrate 1. A crossover 22 consisting of a wiring conductor 19 formed on the first N ⁺ type diffusion layer with an insulating film 17 interposed therebetween, and a crossover 22 formed on the N ⁺ type buried layer so as to be partially in contact with the P type semiconductor substrate. N is formed and whose sides are in contact with one side of the first N ⁺ type diffusion layer.
a P-type first base layer 12 selectively formed on the surface of this first collector layer, an N-type first base layer 12 selectively formed on the surface of this first base layer. ⁺ type first emitter layer 16, and second N + type for wiring connection formed on the surface of the junction between the first collector layer 7 and first N ^{+ type} diffusion layer 20, spanning both layers. NPN composed of diffusion layer 15
The transistor 23 is formed on the N ⁺ type buried layer so that a part of the transistor 23 is in contact with the P type semiconductor substrate, and the N type transistor 23 is formed on the N ⁺ type buried layer so that its side is in contact with the other side of the first N + type diffusion layer.
a P-type second emitter layer 10 selectively formed on the surface of the second base layer, a second base layer 5 and a first N ⁺ type diffusion layer 2.
A third N ⁺ type diffusion layer 13 for wiring connection is formed on the surface of the junction of 0 and straddles both layers, and a PNP transistor 21 is composed of a second collector layer 9 and 1. In this structure, an overcoat, an NPN transistor, and a PNP transistor can be formed within one closed separation wall.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a cross-sectional view of the structure of a bipolar integrated circuit according to an embodiment of the present invention, in which the same or corresponding parts as in FIG. 1 are given the same reference numerals. This embodiment differs from FIG. 1 in that the base of the lateral PNP transistor 21,
An N-type diffusion layer 20 with a high concentration of N-type impurities is formed in the lower wiring of the crossover 22 to which the collector of the NPN transistor 23 is to be connected.
0, an N-type diffusion layer 13 that is connected to the N-type diffusion layer 20 and becomes the base of the lateral PNP transistor 21, and an N-type diffusion layer 15 that becomes the collector of the NPN transistor 23 are formed at both ends of the N-type diffusion layer 20. It is intended to form the overcoat 22, the PNP transistor 21, and the NPN transistor 23 within one closed P-type separation wall 8. In this case, the N-type diffusion layer 20 serving as the lower wiring of the crossover 22 is formed by selectively performing P-type diffusion into the N-type epitaxial layer formed on the P-type substrate 1 to form the P-type separation layer 8. A relatively deep N-type diffusion is formed between the step of forming the P-type diffusion layers 9, 10, and 12 of each PNP transistor 21 and NPN transistor 23,
A diffusion layer having a layer resistance value of several Ω/□ can be easily obtained. Therefore, the layer resistance of the lower wiring of the crossover 22 can be reduced. Note that the N type diffusion layer 20 is connected to its N ⁺ buried layer 3, and this N ⁺ buried layer 3 reduces the base resistance of the lateral PNP transistor 21 and the collector resistance of the NPN transistor 23, respectively. N ⁺ buried layers 2 and 4 are connected.

According to the above-mentioned embodiment, an N-type diffusion layer 20 with a high impurity concentration is formed in the lower wiring of the crossover 22, and N-type diffusion layers 20, which serve as the bases of the lateral PNP transistors 21, are formed at both ends of the N-type diffusion layer 20, respectively. By directly connecting the N-type diffusion layer 13 and the N-type diffusion layer 15 serving as the collector of the NPN transistor 23, there is no need for a conventional connection using the wiring conductor 18 that connects the base and collector of both transistors. In addition, the N-type diffusion layer 20 is used not only as the lower wiring of the crossover 22 but also as the base of the lateral PNP transistor 21 and the NPN
It acts as a collector of the transistor 23, and the base resistance of the PNP transistor 21 and the collector resistance of the NPN transistor 23 become small. Moreover, with these crossover 22
PNP transistor 21, NPN transistor 23
Since there is no separation wall 8 between them as in the conventional case, the lateral PNP transistor 21 and the NPN transistor 2
3 and the crossover 22 will have a very small combined area. Furthermore, the N type diffusion layer 2
Since the diffusion process of 0 is performed before the diffusion process of P type diffusion layers 9, 10 and 12 forming both transistors 21 and 23, the insulating film between the N type diffusion layer 20 and the wiring conductor 19 is The insulating film 17 on the N-type epitaxial layers 5 and 7 is thicker than the conventional insulating film between the P-type diffusion layer 11 and the wiring conductor 19.
The difference between the two becomes smaller. Therefore, the wiring conductor 19
It is possible to prevent the conductor from being cut at the stepped portion of the insulating film 17, and therefore, there is an advantage that the insulating film is not easily damaged even when a surge voltage is applied to this conductor.

Note that in the above embodiment, the PNP transistor 2
1 shows the case where a lateral PNP transistor is used, but a substrate PNP transistor as shown in FIG.
A similar effect can be obtained using a PNP transistor.

As explained above, according to the present invention, N
Forming N-type diffusion layers directly connected to the N-type diffusion layers at both ends of the N-type diffusion layer, providing a PNP transistor with one of them as a base, and providing an NPN transistor with the other as a collector,
These crossovers and PNP transistors and
Since the NPN transistor is formed within one closed separation wall, the layer resistance of the lower wiring of the crossover can be reduced. Furthermore, since there is no separation wall between the crossover and the PNP transistor and NPN transistor, the overall area can be reduced. Furthermore, the base resistance of the PNP transistor and the collector resistance of the NPN transistor become smaller, and the insulation film of the crossover is thicker, and the difference in thickness with the insulation film on the N-type epitaxial layer becomes smaller. It is extremely effective in improving characteristics and reliability, as the step difference is small, the wiring conductor does not break at this step, and the insulating film is less likely to be damaged even if a surge voltage is applied to the wiring conductor. be.

[Brief explanation of the drawing]

FIG. 1 is a structural cross-sectional view of a conventional bipolar integrated circuit, FIG. 2 is a structural cross-sectional view of a bipolar integrated circuit according to an embodiment of the present invention, and FIG. 3 is a structural cross-sectional view of another embodiment of the present invention. It is. 1... P-type silicon single crystal substrate, 2, 3, 4
... N ⁺ buried layer, 5, 7 ... N type epitaxial layer, 8 ... Separation wall 9, 10, 12 ... P type diffusion layer, 13 ... N type diffusion layer which becomes the base of the PNP transistor, 15... N-type diffusion layer that becomes the collector of the NPN transistor, 18, 19... Wiring conductor, 20... N-type diffusion layer forming the lower wiring of the crossover, 21... Lateral PNP
Transistor, 22...Crossover, 23...
NPN transistor.

Claims (1)

[Claims] 1. A first N ^{+ type diffusion layer formed on an N + type} buried layer formed on a P type semiconductor substrate, and an insulating film on this first N ⁺ type diffusion layer. a crossover consisting of a wiring conductor formed through a
an N ^- type first collector layer formed on the N ⁺ -type buried layer and whose sides are in contact with one side of the first N+-type diffusion layer; a P-type first base layer formed on the surface of the first base layer;
A first N ⁺ type emitter layer, and a second wiring connection layer formed on the surface of the junction between the first collector layer and the first N ⁺ type diffusion layer, spanning both layers.
an NPN transistor composed of an N ⁺ type diffusion layer;
an N ^- type second base layer formed on the N ⁺ -type buried layer and whose sides are in contact with the other side of the first N+-type diffusion layer; a P-type second emitter layer formed on the second base layer and the first N ⁺ type diffusion layer, and a third N emitter layer for wiring connection formed on the surface of the junction between the second base layer and the first N + type diffusion layer, spanning both layers. 1. A semiconductor integrated circuit comprising ^{a +} type diffusion layer and a PNP transistor comprising a second collector layer. 2 The PNP transistor uses a P-type collector layer selectively formed on the surface of the second base layer as the second collector layer.
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a PNP transistor. 3. The semiconductor integrated circuit according to claim 1, wherein the PNP transistor is a substrate PNP transistor using a P-type semiconductor substrate as the second collector layer.