JPH02102554A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable an integrated circuit to be not only highly integrated but also operable at a high speed by a method wherein a part of an element isolating groove is made to serve as a wiring without deteriorating the groove in isolating function. CONSTITUTION:Two or more grooves 16, whose base and side are covered with an insulator 17, are provided onto the surface of a semiconductor substrate 11 extending in a longitudinal and a lateral direction, and a semiconductor region is isolated by the grooves 16 to serve as element regions 13 to house elements. A part of the grooves 16 is filled with insulator or genuine polycrystalline silicon 18, and the rest of the grooves 16 is filled with polycrystalline silicon 18a or a filler of other conductive substance whose surface is at least high in impurity concentration. The polycrystalline silicon 18a or the other conductive substance of high impurity concentration is connected to the electrodes of a part of elements formed in the element regions. By this setup, a semiconductor device of this design can be made operable at a high speed without being prevented from being highly integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a trench isolation type semiconductor integrated circuit in which each element is separated by a clear line.

[Prior art] In recent bipolar random access memories,
In order to meet the ever-increasing demands for higher integration and higher speed, oxide-separated types and groove-separated types are being used.

In this trench isolation type semiconductor integrated circuit, a trench whose inner surface is covered with an insulator is formed on one main surface of the semiconductor substrate, and the semiconductor element regions are separated by this trench. The inside of the trench is filled with an insulator or intrinsic polysilicon up to the surface level of the semiconductor substrate. In addition, in this type of S product circuit, aluminum is generally used for wiring that connects electrodes of semiconductor elements.

[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit described above, the size of the wiring has been reduced in order to increase the A. In addition, since the wiring capacitance is reduced, it is advantageous for speeding up the operation. However, when the wiring width is reduced, a large current cannot be passed through the wiring because the voltage drop in the wiring becomes too large or causes electromigration. For this reason, in bipolar integrated circuits that are designed to operate at higher speeds by passing large currents through them, the higher degree of integration has become an impediment to higher operating speeds. Further, as the wiring width becomes narrower, the wiring resistance increases, which also impedes the speeding up of the operation. One possibility is to increase the thickness of the wiring to lower the wiring resistance and increase the current capacity, but this will worsen the flatness of the board surface and cause the upper layer wiring to become disconnected. There is a risk that this may occur.

The present invention has been made in view of the above points, and its purpose is to provide low resistance wiring without sacrificing the density of integrated circuits. The goal is to achieve both high integration and high speed in integrated circuits.

[Means for Solving the Problems] In the semiconductor integrated circuit of the present invention, a plurality of grooves extending in the vertical and horizontal directions and whose bottom and side surfaces are covered with an insulating material are formed on the surface of the semiconductor substrate. The semiconductor region separated by the trench accommodates an element as an element region, and some of the trenches are
The interior of the groove is filled with an insulating material or intrinsic polycrystalline silicon, and the other trenches are filled with a filling material whose interior is polycrystalline silicon or other conductive material with a high impurity concentration at least in its surface portion. ing. Then, some electrodes of the element formed in the element region are connected to this polycrystalline silicon or other conductive material having a high impurity concentration.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing an embodiment of the present invention, and shows an example of a bipolar S RAM memory cell. As shown in the figure, the groove 16 extends in the vertical and horizontal directions, and the side walls and bottom surface (not visible in this figure) of the groove are covered with an oxide film 17. Therefore, the element regions 13 separated by the grooves are eventually surrounded by the oxide film 17.

The pure area is filled with intrinsic polycrystalline silicon 18 to the same height as the semiconductor substrate surface, but some of this polycrystalline silicon is doped with a large amount of boron and becomes P"
It is made of polycrystalline silicon 18a.

A bipolar transistor having a base 20, a collector 22, and two emitters 21, a load resistor 24, and a Schottky barrier diode 23 are formed in the element region 13, and a flip-flop is formed by the elements in the two element regions. The type of memory cell is configured.

The emitters of the two transistors are each connected to a separate P1 polycrystalline silicon 18a, which acts as a digit line.

Next, the manufacturing method of this example will be explained.

FIGS. 2(a) to 2(e) are cross-sectional views of the main manufacturing steps of this embodiment.

First, as shown in FIG. 2(a), a P-type semiconductor substrate 11
A buried layer 12 for a memory cell transistor region is formed thereon, and an n-type epitaxial layer 13a having a resistivity of 5 Ω1 is grown to a thickness of 1 μm thereon. And epitaxial 7! A nitride film 14 with a thickness of 0.1 μm is grown on the l 13a, and a resist 15 is applied on the upper surface.Next, as shown in FIG. 2(b), the resist 15 is exposed and developed. Then, the nitride film 14 is patterned. Then, using this nitride film 14 as a mask, the epitaxial layer 13a is selectively etched down to the P-type semiconductor substrate 11 to form a groove 16 and separate the element region 13.

Next, as shown in FIG. 2(c), after removing the nitride film 14, the bottom and wall surfaces of the groove 16 and the surface of the element region 13 are thermally oxidized at 1000° C. for 10 minutes to remove the oxide film 17. Next, as shown in FIG. 2(d), the groove 16 is filled with intrinsic polycrystalline silicon 18 so that its height is approximately equal to the surface of the semiconductor element region 13.

Subsequently, a nitride film 19 is formed on the upper surface of the wafer, which has a substantially flat surface. And what about the polycrystalline silicon part where you want to lower the resistance? The nitride film 19 on the upper surface of 1116 is selectively etched away. Then, boron is diffused into polycrystalline silicon at a high concentration. Thus, as shown in FIG. 2(e), the desired edge 16 is filled with P+ polycrystalline silicon,
A structure in which the other trenches 16 are filled with intrinsic polysilicon 18 is obtained.

After this, elements are formed in the element region 13 using a normal method, and wirings connecting the elements are formed. that time,
The above-mentioned P+ polycrystalline silicon 18a is used for part of the wiring connecting elements.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view showing an intermediate stage in manufacturing this embodiment, and corresponds to the process shown in FIG. 2(e). The one shown in FIG. 3 is formed through the same steps as in the previous embodiment up to the stage of FIG. 2(d), and then the nitride film 19 is selectively removed to expose the After etching the polycrystalline silicon 18 thinly, platinum is deposited thereon. Thereafter, heat treatment is performed to form platinum silicide (PtSi) 18b in this portion. In this case, by adjusting the etching amount of polycrystalline silicon and the deposition thickness of platinum, the upper surface of platinum silicide 18b is made to substantially match the surface height of the semiconductor substrate. According to this embodiment, a wiring having lower resistance than the previous embodiment can be obtained.

[Effects of the Invention] As explained above, the present invention uses a part of the element isolation trench, which has conventionally been used only for isolating elements, for wiring without impairing the isolation effect. Since the resistance value of this wiring can be made sufficiently low, according to the present invention, high-speed operation can be achieved without hindering the high integration of the integrated circuit. Further, even if the wiring is used in a place where a large current flows, the voltage drop can be kept within an allowable range for the operation of the device.

[Brief explanation of drawings]

FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
) to (e) are cross-sectional views of the manufacturing process of the embodiment shown in FIG. 1, and FIG. 3 is a cross-sectional view for explaining another embodiment of the present invention. 11...P-type semiconductor substrate, 12...buried layer,
13... Element region, 13a... Epitaxial layer, 14... Nitride film, 15... Resist, 1
6... Groove, 17... Oxide film, 18... Intrinsic polycrystalline silicon, 18a... P+ polycrystalline silicon, 18
b...Platinum silicide, 19...Nitride film.

Claims (1)

[Claims] A semiconductor integrated circuit in which a groove whose inner surface is covered with an insulator extends vertically and horizontally in one principal surface of a semiconductor substrate, and elements are formed in semiconductor element regions separated by the groove. In the circuit, a part of the trench is filled with insulator or intrinsic polycrystalline silicon, and another part of the trench is filled with polycrystalline silicon or other conductive material with at least a surface portion thereof having a high impurity concentration. and a part of the electrode of the device formed in the semiconductor device region is connected to the polycrystalline silicon having a high impurity concentration or the conductive material. Semiconductor integrated circuit.