JPH02266530A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance of a collector in a bipolar transistor by a method wherein isolation between elements is performed by a first region contiguous from a substrate and a second region having reverse conductivity while the second region is electrically connected to the collector region. CONSTITUTION:A vertical bipolar transistor comprising a collector region 6 having first conductivity, a base region 8 having second conductivity and an emitter region 9 having first conductivity is formed on an imbedded layer 2. An element isolating region for isolating elements is constituted of a first region 10 and a second region 3 having reverse conductivities to have pn junction separated, and the second region 3 having the same conductivity as the imbedded layer 2 contiguous from the imbedded layer 2 to the surface is electrically connected with a collector region 6 to have them shorted. Thus parasitic capacitance between the collector region and the second region and the imbedded layer is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a vertical (particle type) bipolar transistor.

[Summary of the Invention] The present invention provides a semiconductor device 1 in which a vertical bipolar transistor is formed on a buried layer. The parasitic capacitance in the collector region can be equivalently reduced by separating the elements by a first region that is continuous from the substrate to the surface of the substrate, and electrically connecting the second region to the collector region. be.

[Conventional technology]

As an example of a semiconductor device, a device in which a bipolar transistor is formed on a semiconductor substrate made of silicon or the like is widely known. Due to its structure, this bipolar transistor has
Some devices are formed vertically, and have an element structure as shown in FIG. 4, for example.

FIG. 4 is a sectional view showing an example of a device having a conventional bipolar transistor. An n-type buried layer 102 is formed on a p-type silicon substrate 101, and an n-type epitaxial layer 103 is stacked thereon. A vertical pnp bipolar transistor is formed on the buried layer 102.

The collector region is composed of a p-type impurity region 104 formed from the n-type buried layer 102 to the epitaxial layer 103, and a p-type extraction region 105 formed from the impurity region 104 to the substrate surface. Ru. The base region is the n of the substrate surface surrounded by the collector region.
The type impurity diffusion $■ region 106, and the emitter region is
It is constituted by a p-type impurity diffusion region 107 formed within the impurity diffusion region 106.

Further, the isolation between the elements is achieved by pn junction isolation, and the pn junction between the p-type region 108 that continues from the p-type silicon substrate 101 to the substrate surface and the n-type epitaxial layer 103 is established. is used. For this reason
The potential of the type epitaxial layer 103 is equal to the power supply voltage Vcc
The extraction region 109 is formed on the surface of the substrate.

C. Problems to be Solved by the Invention] In the semiconductor device having the above-described structure, in order to perform element isolation, the epitaxial layer 103 is supplied with the power supply voltage Vcc, which is the highest potential.

However, by supplying the power supply voltage Vcc to the epitaxial layer 103 in this way, a parasitic capacitance is created between the impurity region 104 and extraction region 105 that constitute the collector region, and the n-type epitaxial layer 103 and the n-type buried layer 102. will occur. In particular, this parasitic capacitance has a large capacitance value because the impurity concentration in the collector extraction region 105 is high, and the frequency characteristics of the bipolar transistor eventually deteriorate.

SUMMARY OF THE INVENTION In view of the above-mentioned technical problems, it is an object of the present invention to provide a semiconductor device that reduces the parasitic capacitance of the collector of a bipolar transistor.

[Means to solve the problem]

In order to achieve the above object, the semiconductor device of the present invention has the following features:
A buried layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and includes a collector M region of the first conductivity type, a base region of the second conductivity type formed in the head region of the collector, and a base region of the collector M region of the first conductivity type. A vertical bipolar transistor including an emitter region of a first conductivity type formed within the buried layer is formed on the buried layer. The isolation between each element is provided by a second GL region of a second conductivity type that is continuous from the buried layer to the substrate surface and electrically connected to the collector region, and a second GL region of the second conductivity type that is electrically connected to the collector region; and a first region of the first conductivity type that is continuous from the substrate to the surface of the base body.

[Effect]

Pn junction splitting is performed by configuring an element isolation region for element isolation with a first region and a second region of opposite conductivity type. The parasitic capacitance between the collector region, the second region, and the buried layer is reduced by electrically connecting and short-circuiting the second region continuous to the collector region.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment This embodiment is an example of a semiconductor device having a vertical pnp bipolar transistor.

On a p-type silicon substrate 1, whose cross-sectional structure is shown in FIG. 1, an n-type buried N2 is formed corresponding to the active region of the element. On this buried layer 2, an n-type epitaxial layer 3 is laminated and formed. This n-type epitaxial layer 3 is a region outside the collector of the bipolar transistor and functions as a second 6M region for element isolation.
A take-out region 4 for short-circuiting with the collector is formed in a part of the surface of the base.

A p-type impurity region 5 is formed over the epitaxial layer 3 so as to overlap the n-type buried layer 2 above it. This p-type impurity region 5 functions as a collector region of a pnp bipolar transistor. This p-type impurity region 5 is continuous with a collector extraction region 6 formed from the impurity region 5 to the substrate surface. A collector electrode is connected to this collector extraction region 6.

Inside the p-type impurity region 5 functioning as a collector and the collector extraction region 6, an epitaxial layer 3 is formed.
This remaining n-type epitaxial region 7 is surrounded by a p-type impurity region 5 and a core/output extraction region 6. Further, inside the remaining epitaxial region 7, a base region 8 made of an n-type impurity region is formed facing the substrate surface. This base region 8 is connected to the base electrode at its substrate surface. Then, an emitter region 9 made of a p-type impurity region is formed inside the base region 8 so as to similarly face the substrate surface. An emitter electrode is also formed on this emitter head mount 9 on the surface of the substrate. These emitter regions9. The positional relationship between the base region 8° and the p-type impurity region 5 serving as the collector region is perpendicular to the main surface of the substrate. With i1M, a vertical pnp bipolar transistor is obtained on the substrate.

Element isolation of a semiconductor device having this vertical pnp bipolar transistor is performed by pn junction isolation, and specifically, the n-type epitaxial layer 3, which is the second region, and the semiconductor device disposed between the adjacent elements. This is done by a p-type isolation region 10 as a first region. Here, the n-type epitaxial layer N3 is formed outside the collector of the bipolar transistor, and the n-type epitaxial layer N3 is formed on the bottom of the bipolar transistor collector.
The layer is continuous from the buried layer 2 of the mold to the surface of the substrate. On the base surface of the epitaxial layer 3, a take-out region 4 for supplying a potential is formed as described above, and this take-out region 4 is electrically connected to the collector region via a collector electrode.

FIG. 3 is an equivalent circuit of the collector portion of a pnp bipolar transistor. Explaining based on FIG. 3, the node 51 corresponds to the collector region, and the node 52 corresponds to the n-type epitaxial layer 3 and the n-type buried layer 2, which are the second regions.

Further, the grounded node 53 is connected to the p-type silicon substrate 1
and corresponds to the p-type isolation region IO. There is a parasitic capacitance 55 between the node 51 and the node 52;
A parasitic capacitance 56 also exists between the node 53 and the node 53 . Above n
If the epitaxial layer 3 of the mold is connected to the collector via the extraction region 4, it will be short-circuited as shown by the wiring 54. As a result, the parasitic capacitor 55 no longer functions as a capacitor because the potentials at both ends thereof are equal.

As is clear from FIG. 3, the epitaxial layer 3
The potential of the collector becomes in phase with that of the collector due to the collector potential supplied via the extraction region 4. As a result, the parasitic capacitance between the collector region and the epitaxial layer 3 and the n-type buried layer 20 is reduced equivalently, and the parasitic capacitance of the pnp bipolar transistor is reduced between the isolation region 10 and the p-type buried layer 20, which have relatively small capacitance values. There is only a capacitance between the silicon substrate 1, the epitaxial layer 3, and the n-type buried layer 2.

This reduced parasitic capacitance of the pnp bipolar transistor has a capacitance value equivalent to that of a highly doped npn bipolar transistor without collector extraction, and the capacitance is about 0.6 times that of the conventional example (Figure 4). It will be reduced.

Second Embodiment This embodiment is an example in which both a vertical pnp bipolar transistor and a lateral npn bipolar transistor are formed on the same silicon substrate.

The cross-sectional structure of the transistor is shown in FIG. A mold embedding layer 22 is formed. On this buried layer 22, an n-type epitaxial layer 23 is laminated and formed. This n-type epitaxial layer 23 is pn
In the region outside the collector of the p-bipolar transistor,
A take-out region 24 is formed in a part of the base surface to function as a second region for element isolation and to short-circuit with the collector.

The n-type buried layer 22 has a p-type layer overlapping it on the upper side.
A type impurity region 25 is formed across epitaxial layer 23 . This p-type impurity region 25 is the impurity region 2
5 to the collector take-out region 26 formed from the substrate surface.

A collector electrode is connected to the collector extraction region 26. The collector extraction region 26 and the p-type impurity region 25 function as a collector region. A part of the epitaxial layer 23 remains inside the p-type impurity region 25 and the collector extraction region 26 that function as collectors, and the n-type remaining epitaxial region 27 is
It is surrounded by a mold impurity region 25 and a collector extraction region 26 . Further, inside the remaining epitaxial region 27, a base head M'28 made of an n-type impurity region M is formed facing the substrate surface. And its base area 28
Similarly, an emitter region 29 made of a p-type impurity region is formed inside the substrate, facing the surface of the substrate. These base areas 28. A base capacitor and an emitter electrode are formed in the emitter region 29, respectively.

Next, the structure of the npn bipolar transistor 30 is such that an n-type buried layer 22 is formed on a p-type silicon substrate 21 in the active region of the Blnpn bipolar transistor 30, and a layer is laminated on top of the buried layer 22. n-type epitaxial Il! A collector region 31 is formed on the surface of the substrate 23. The base area 32 is the collector area 3
1 is formed in an n-type epitaxial layer 23 facing the substrate surface at a position spaced apart from the substrate surface. This base region 32 consists of a p-type impurity region. Inside the base region 32 is an emitter region 33 facing the substrate surface.
is formed. These collector areas 31° base areas 3
2. The emitter region 33 is arranged laterally on the substrate surface,
A horizontal npn bipolar transistor 30 is configured.

Isolation between the npn bipolar transistor 20 and the pnpn bipolar transistor 30 is performed by a pn junction between the p-type isolation region 34, which is the first region, and the n-type epitaxial layer 23. Here, the p-type isolation region 34 is formed continuously from the p-type silicon substrate 21 to the base surface, and is formed in the n-type epitaxial layer 23 between the elements.
formed to divide the

In the semiconductor device of this embodiment, the n-type epitaxial layer 23 of the pnp bipolar transistor 20 is electrically connected to the collector region via the extraction region 24 and short-circuited. The parasitic capacitance between the n-type buried layer 22, the collector extraction region 26, and the p-type impurity region 25 is equivalently reduced. Therefore, deterioration of the frequency characteristics of the transistor can be prevented. Further, the parasitic capacitance of the pnp bipolar transistor 20 is the parasitic capacitance of the npnp bipolar transistor 30 and the capacitance value between the lines and the like.

In each of the above-described embodiments, the vertical bipolar transistor is described as being of the pnp type, but the vertical bipolar transistor may also be of the opposite npn type.

〔Effect of the invention〕

In the semiconductor device 1 of the present invention, element isolation is performed by a first region continuous from the substrate and a second region of the opposite conductivity type, and the second region is electrically connected to the collector region. Therefore, the capacitance between the collector region and the second region is reduced, and the frequency characteristics of the bipolar transistor are improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the element structure of an example of the semiconductor device of the invention, FIG. 2 is a sectional view showing the element structure of another example of the semiconductor device of the invention, and FIG. FIG. 4 is a circuit diagram showing the relationship of parasitic capacitance in a bipolar transistor portion, and is a cross-sectional view of an example of a conventional semiconductor device. 1.21...Silicon substrate 2.22...Buried layer 323...Epitaxial layer 4.24...Takeout region 5.25...Impurity region 6.26...Collector takeout region 828...・Base region 9.19...Emitter region 10.34...Isolation region

Claims (1)

[Claims] A buried layer of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and includes a collector region of the first conductivity type, a base region of the second conductivity type formed within the collector region, and a base region of the second conductivity type formed within the collector region. A vertical bipolar transistor is formed on the buried layer, and has a second conductive type, which is continuous from the buried layer to the substrate surface and electrically connected to the collector region. Type 2
and a first region continuous from the semiconductor substrate to the base surface.
A semiconductor device characterized in that element isolation is performed by a first region of a conductive type.