JPS6045032A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent any parasitic effect perfectly and easily by a method wherein an inverse conductive type contact region provided outside a vertical type P-N-P transistor of the first island region and a collector region of the vertical type P-N-P transistor are electrically connected. CONSTITUTION:A one conductive type semiconductor substrate 21, an inverse conductive type epitaxial layer 22 deposited on the substrate 21, another one conductive type separation region 25 vertically separating the epitaxial layer 22 into two island regions 23, 24, a vertical type P-N-P transistor 32 provided on the first island region 23 and an adjoining second island region 24 are provided while another inverse conductive type contact region 33 is provided outside the vertical type P-N-P transistor 32. Then a collector electrode 34 of said transistor 32 is extended making itself come into ohmic contact with the contact region 33 to electrically connect the collector region 27 of said transistor 32 with the contact region 33. Thus the collector region 27 of the vertical type P-N-P transistor 32 and the epitaxial layer 22 outside said transistor 32 of the first island region 23 may be held at equivalent potential.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit that eliminates the parasitic effects of silage.

(b) Prior Art As shown in FIG. 1, a conventional semiconductor integrated circuit has a P-type semiconductor substrate (1), an N-type epitaxial layer (2) formed on the substrate (9 layers), and an epitaxial layer (2). a P-type separation region (5) that separates the upper and lower regions into island regions (3) and (4);
N+ type buried I provided at the bottom of each island region (3) (4)
I (6) and the P-type collector region (7) formed in the first island region (3) (7) P-type collector lead-out region (8) N-type base region (9) N-type base contact region θ1 and P-type It is composed of a vertical PNP transistor (6) composed of an emitter region α and an N+ type tunnel resistance region q3 formed in an adjacent second island region (4).

In such semiconductor integrated circuits, vertical PNP transistors (2
) is biased to pathological type 1, and the second island region (4) or tunnel resistance region 01 is biased to a low potential, the emitter region (1]) base region (9) collector region (7) P N P N in the first island region (3) isolation region (5) and second island region (4)
A self-biased parasitic thyristor of P N is formed,
Parasitic Lee When Irista turns on, it becomes parasitic as shown by the arrow■
The flow flows.

FIG. 2 is an equivalent circuit diagram of a parasitic thyristor.

Tr is an original PNP transistor formed of the emitter region α base region (9) and collector region (7) of the vertical PNP transistor q, and Try is the space region (9), collector region (7) and The first island region (3) is a vertical PNP transistor (NPN) transistor formed of the outer epitaxial layer of the transistor (2), and the Trl rectifier region (7) the above-mentioned outer epitaxial layer and isolation region. (5) PNP formed by
) transistor, and Tr4 is an NPN ) transistor formed by the aforementioned outer epitaxial layer isolation region (5) and the second island region (4).

In order to effectively prevent such a parasitic thyristor effect, conventionally the epitaxial layer outside the first island region (3) described above was connected to the power supply voltage. However, this method requires routing power lines, which poses an obstacle in terms of the degree of integration.

(c) Purpose of the Invention The present invention has been made in view of the discontinuity, and provides a semiconductor integrated circuit in which parasitic effects can be completely and easily prevented.

B) Structure of the Invention The semiconductor integrated circuit according to the present invention, as shown in FIG. an island region (1 conductivity type separation region vertically separated into (c)), a first island region (vertical PNP provided with fiK) transistor (2), and an adjacent second island region (c) and a vertical PNP transistor (2) in the first island region.
A contact region of the opposite conductivity type is provided outside the transistor, and the contact region is electrically connected to the collector region of the vertical PNPI transistor.

(E) Example In this example, as shown in FIG. 3, an N-type silicon epitaxial layer (A) is formed on a P-type silicon semiconductor substrate, and this epitaxial layer (A) is separated into a P1-type silicon epitaxial layer (A). Separate the upper and lower PNs in the area to form each island area (c).

The bottom of each island region (c) is an N4 type buried layer (c)
is provided. The first island region includes a P-type collector region (I) provided on the buried layer, a P-type collector derivation region (I) that reaches from the surface to the collector region (A), and a base region (I) surrounded by the collector region (I). ), a vertical PNP transistor formed by an N+ type base contact region (1) and a P+ type emitter region OD are provided. In the adjacent second island region (c), the epitaxial layer (a) is used as it is as an epitaxial resistance, or an N-type resistance region (2) is further diffused and used as a tunnel resistance.

The features of the present invention are an N-type contact region and a vertical P-type contact region.
There is a collector electrode (c)K on the transistor (NP). The contact region (to) is the vertical PNP of the first island region)
Provided in the epitaxial moisture on the outside of the transistor (c),
They may be provided so as to surround the vertical PNP transistor) or may be provided in a scattered manner. Also, the contact area (
If 2) is diffused sufficiently deeply, at least to the same depth as the contact point lead-out region, a sufficient contact can be formed and a more sufficient effect can be obtained. Then, the collector electrode (c) of the vertical PNP transistor 02 is expanded and made into ohmic contact with this contact region, and the vertical PNP)
Electrical connection is made between the collector region (A) of the transistor (2) and the contact region. According to such a structure, vertical PNP
) The collector region of the transistor (2) and the epitaxial moisture outside the vertical PNP transistor (2) of the first island region can be held at the same potential.

An equivalent circuit diagram of the structure of the present invention described above is shown in FIG. In Fig. 4, Trl, Trt, TrB, Tr4
is the same as in Figure 2, and the pace of Tr and Tr
The feature is that the emitter of No. 4 is short-circuited. As a result, since ■□ is not applied to Tr and Trs, this parasitic thyristor is not turned on, and parasitic effects can be completely prevented.

(F) Effects of the Invention According to the present invention, parasitic thyristor effects can be reliably prevented even if the structure is the same as the conventional one only in the contact region. As a result, the degree of integration of the semiconductor integrated circuit can be maintained as it is. In addition, there is no need for special wiring of the electrodes, and this can be achieved only by expanding the collector electrode, so it is easy to use the electrode pattern as a film. Furthermore, since it can be manufactured using the same manufacturing process as the conventional one, it can be implemented immediately without requiring any change in the manufacturing process.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining a conventional example, FIG. 2 is an equivalent circuit diagram for the conventional example, FIG. 3 is a sectional view for explaining the present invention, and FIG. 4 is an equivalent circuit diagram for the present invention. Explanation of main drawing numbers QI) is the semiconductor substrate, (a) is the epitaxial layer, the top is the first island region, the south is the second island region, ni) is the isolation region, the trunk is the vertical PNP) transistor, The eel is the contact region, and (c) is the collector electrode. Figure 10 2 in Figure 3

Claims (1)

[Claims] (1) A first island comprising a semiconductor substrate of -4 conductivity type, an epitaxial layer of opposite conductivity type provided on the substrate, and a separation region of one conductivity type that separates the epitaxial layer into a plurality of island regions. In a semiconductor integrated circuit in which a thyristor parasitic effect occurs between a vertical PNP transistor provided in a region and an adjacent second island region. A semiconductor integrated circuit characterized in that a contact region of an opposite conductivity type is provided outside the vertical PNP transistor in the first island region, and the contact region is electrically connected to a collector region of the vertical PNP transistor. circuit.