JPS61280661A - Transistor - Google Patents

Abstract

PURPOSE:To realize a minimum pattern size without affecting hPE, by providing a first region of an N<+> type on the entire surface of an insular region except for a base region. CONSTITUTION:A first region 29 of an N<+> type is provided on the entire surface of an insular region 25 except for a base region 26. According to this structure, a distance A can be shortened further without lowering rho of an epitaxial layer 22. Since regions 24, 26 and 29 are formed by thermal diffusion from the surface of the insular region 25, junctions of these regions are curved by diffusion in the lateral direction. Therefore, a distance between junctions of base-collector and collector-separation is minimum on the surface (distance A) and becomes large gradually as the junctions deepen, and thus the junctions are separated sufficiently by a distance B in the bottom portion of the first region 29. Depletion layers 35 spreading in each junction are curbed in the first region 29 of this concentration to be narrower than the ones in other regions. In other words, the first region 29 suppresses the spread of the depletion layers 35 on the surface of the insular region 25, while a sufficient separation is attained, as described above, in deeper regions, and thus the distance A can be shortened by an amount of the spreading being suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in transistors incorporated in low-voltage semiconductor integrated circuits powered by batteries, for example.

(B) Prior Art Conventionally, as a transistor incorporated into a semiconductor integrated circuit (IC), there is one described, for example, in Japanese Patent Application Laid-open No. 189665/1983.

That is, as shown in FIG. 3, a buried layer of an N-type epitaxial layer (2) formed on a P-type semiconductor substrate +11 and an N-type buried layer (3) provided on the surface of the substrate (1). (3)
A P+ type isolation region (4) penetrating the epitaxial layer (2) surrounding the epitaxial layer (2), an island region (5) separated into islands by the isolation region (4), and an island region (5) formed on the surface of the island region (5). P
The base region (6) of the mold, the Nu emitter region (7) formed on the surface of the base region (6), and the epitaxial layer (
2) Oxide film (8) covering the surface and this oxide film (8)
It consists of a collector electrode αα, a base electrode αD, and an emitter electrode Cl21, which are in ohmic contact with the collector contact region (9), base region (6), and emitter region (7), respectively, through the electrode holes of the island region (5). An NPN type transistor is configured as a collector.

When incorporated into a normal IC, the withstand voltage (Vc,

, Vc 5un) of approximately 40V, the distance between the pace region (6) and the separation region (4) (A in the figure) is 1.
0μ or more was required.

When incorporating the transistor configured as described above into a low-voltage IC, the inventor of the present application considered lowering the resistivity ρ of the epitaxial layer (2) (increasing the impurity concentration) for the purpose of reducing the distance. In other words, since a low-voltage IC does not require a very high breakdown voltage, lowering ρ of the epitaxial layer (2) suppresses the spread of the depletion layer that occurs at the pace-collector junction and the collector isolation junction, and reduces the distance A. This is to reduce the pattern size of the island region (5). As a result, the withstand voltage decreases.

There is no problem as a low voltage IC.

e→ Problems to be solved by the invention However, in the above method, the epitaxial layer (2
) has the disadvantage that hFl of the transistor will vary if the ρ of ) is lowered too much, and furthermore, a parasitic effect is likely to occur due to the parasitic PNP transistor formed by the space region (6), the island region (5), and the substrate (IJ). was there.

B) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and provides a low-voltage transistor that achieves the minimum pattern size without affecting h□ and prevents parasitic effects. The purpose is to
N type 1 on the egg surface in all island regions except base region 4.
A region is provided, and a P type isolation region Q is provided for the N type buried layer.
It is characterized by expanding until it touches 4J.

(E) Effect According to the present invention, it is possible to suppress the spread of the depletion layer on the surface of the island region □□□ without changing ρ of the epitaxial layer Q2, and furthermore, the collector resistance rc of the NPN transistor can be reduced. , the parasitic effect can be prevented by the synergistic effect of lowering hFl of the parasitic PNP transistor based on the buried layer (c).

(f) Example The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment according to the present invention, in which an N-type epitaxial layer formed on a P-type semiconductor substrate J is separated from the substrate (P-type isolation region c!4 reaching up to 211) from the surface of the epitaxial layer. An island region (C) electrically isolated from other regions by region +241, and an N region embedded in the bottom of the island region (C) and expanded until it comes into contact with the isolation region (goods).
The mold buried layer (to), the P type base region formed on the surface of the island region ■, the N type emitter region @ formed on the surface of the space region 4, and all the island regions 251 except the space region (4).
An N-type first region formed on the surface and an oxide film covering the epitaxial layer (22).

It is composed of one electrode (311c) which makes ohmic contact with @2 in each region through an electrode hole formed in the oxide film. The island region (c) is a collector, and is led out by the electrode □□□ with the first region (to) as the collector contact. The value of ρ of epitaxial layer 4 is the same as that of the conventional one, and the first region (c) is the emitter region (5).
At the same time, it is formed by diffusion.

The first feature of the present invention is that N-type first regions are provided on the surfaces of all the island regions (C) except for the base region 4. According to this structure, the distance A can be further reduced without lowering the ρ of the epitaxial layer (22+).This will be explained in more detail below.

Figure 2 is a cross-sectional view showing how the depletion layer spreads.
The figure shows a pace area (c), a separation area (to), and a first area formed on the surface of the island area. Since these regions C(a) □□□4 are formed by thermal diffusion from the surface of the island region, the junction of each region is curved as shown in the figure due to lateral diffusion, thereby separating the base and collector. The distance between the junctions is the smallest at the surface (distance A), and gradually increases as the junctions become deeper, and at the bottom of the first region, they are sufficiently separated by a distance B. The depletion layer C35 which spreads in each junction is suppressed in the first region of high concentration as indicated by the dotted line in the figure, and becomes narrower than that in other regions.

That is, according to the present invention, on the surface of the island region (c), the first region ridge suppresses the spread of the depletion layer c (51), and in the deeper region, as described above, the first region ridges are sufficiently spaced apart.
The distance A can be reduced by the amount by which the spread is suppressed. However, the first region device has a diffusion depth that is sufficient to obtain a sufficient distance B, and the value of the breakdown voltage (Vclo, YesUs), which is lowered by suppressing the spread of the depletion layer G9 (g), is lower than the working voltage. It is necessary to set the impurity concentration so that it does not occur. The inventor of the present application formed the first region (C) using a diffusion process of the emitter region (5) to satisfy these two conditions, and achieved a breakdown voltage of 7V and a distance A of 5μ or less.

The second feature of the present invention is that the isolation region 2 of the buried layer
It is at the point where it expands until it touches 4). According to this structure, the injection is performed from the emitter region (3) and the collector region (
All the carriers that cannot be captured in (b)) will be captured in the buried layer (c), so the parasitic PNP with the island region (c) as a pace decreases the h□ of the transistor, and the buried layer [ ] and by making the first region 4 a collector contact, the collector resistance rc decreases, so the Vcw (s a t
) becomes lower. That is, h of the parasitic PNP transistor
□ decreases and Vat(Sa) of NPN transistor
Due to the synergistic effect of lowering t), parasitic effects can be almost completely prevented. Here, embedded layer profit and separation area c! Since the junction with the leak is a junction in a high concentration region, the withstand voltage (Vc-, . . . ) is lowered, but there is no problem in using it for low voltage.

It goes without saying that the first region can be formed not only by using the emitter diffusion process but also by controlling the impurity concentration and diffusion depth in a separate diffusion process, so that the breakdown voltage and the distance A can be arbitrarily set.

(g) As described in detail, the present invention has the advantage that the distance can be reduced to the maximum extent, thereby reducing the pattern size of the island region 4 and achieving higher integration.

In addition, since the ρ of the epitaxial layer 2 is not lowered, there is an advantage that 8 is not lowered, and furthermore, the collector resistance rc
decreases, so Vcg (sat) becomes low, and ■. (m
ax) becomes large, and there is an advantage that parasitic effects can be almost completely prevented. The present invention does not require any extra steps, and therefore can be implemented immediately without changing conventional processes, and has the advantage that a low-voltage IC with reduced chip area and good characteristics can be easily realized. .

[Brief explanation of drawings]

FIGS. 1 and 2 are sectional views illustrating a transistor according to the present invention, and FIG. 3 is a sectional view illustrating a conventional transistor. Explanation of the basic drawing numbers (IIcI!11 is a P-type semiconductor substrate, (31G!31 is an N-type buried layer. The mold base area and the vessel are the first area. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuka Sano Mistake 1 Figure 2

Claims (1)

[Claims] (1) Separated into islands by an epitaxial layer of opposite conductivity type formed on a semiconductor substrate of one conductivity type, a buried layer of opposite conductivity type provided on the surface of the substrate, and an isolation region of one conductivity type penetrating the epitaxial layer. In the transistor, the transistor includes an island region formed on the surface of the island region, a base region of one conductivity type formed on the surface of the island region, and an emitter region of the opposite conductivity type formed on the surface of the base region. A parasitic effect is prevented by providing a first region of opposite conductivity type to reduce the distance between the base region and the isolation region, and expanding the buried layer until it comes into contact with the isolation region. transistor.