CN1003334B - Bipolar transistor - Google Patents
Bipolar transistor Download PDFInfo
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- CN1003334B CN1003334B CN86100558.9A CN86100558A CN1003334B CN 1003334 B CN1003334 B CN 1003334B CN 86100558 A CN86100558 A CN 86100558A CN 1003334 B CN1003334 B CN 1003334B
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Abstract
To realize a minimum pattern size without affecting hPE, by providing a first region of an N<+> type on the entire surface of an insular region except for a base region. A first region 29 of an N<+> type is provided on the entire surface of an insular region 25 except for a base region 26. According to this structure, a distance A can be shortened further without lowering rho of an epitaxial layer 22. Since regions 24, 26 and 29 are formed by thermal diffusion from the surface of the insular region 25, junctions of these regions are curved by diffusion in the lateral direction. Therefore, a distance between junctions of base-collector and collector-separation is minimum on the surface (distance A) and becomes large gradually as the junctions deepen, and thus the junctions are separated sufficiently by a distance B in the bottom portion of the first region 29. Depletion layers 35 spreading in each junction are curbed in the first region 29 of this concentration to be narrower than the ones in other regions. In other words, the first region 29 suppresses the spread of the depletion layers 35 on the surface of the insular region 25, while a sufficient separation is attained, as described above, in deeper regions, and thus the distance A can be shortened by an amount of the spreading being suppressed.
Description
The present invention relates to the bipolar transistor in the relevant semiconductor integrated circuit that uses low-voltage, particularly about dwindling this transistorized volume and preventing the problem of parasitic transistor effect.
Technology one example as a setting, the content that the open communique of Japan Patent " according to 59-189665 " is delivered are exactly the bipolar transistor in the semiconductor integrated circuit in the past.
Referring to Fig. 1, it has represented this transistorized in the past longitudinal profile structure.On the surface layer part zone of P type semiconductor substrate 1, form N
+Type buried layer 2 in embedding this buried layer 2, covers on the whole surface of Semiconductor substrate 1 and forms N type epitaxial loayer 3.When surrounding this buried layer, setting connects to the P of Semiconductor substrate 1 from the surface of epitaxial loayer 3
+Type isolated area 4.Just in the collector region 5 that is separated into island by isolated area 4, form transistor.Form P type base 6 on the surface layer part zone in collector region 5, form N on the surface layer part zone in this base 6
+Type emitter region 7.Use the surface of the dielectric film covering epitaxial loayer 3 as oxide-film, by the electrode hole of being opened on this dielectric film 9, make collector electrode 10 base stages 11 and emitter 12 respectively with N
+Type collector contact district 8, base 6 and emitter region 7 contact as resistance.So, just in island district 5, constitute NPN transistor.
This transistor in integrated circuit, for obtain about 40V withstand voltage (VcBo, Vc-suB), the spacing distance A that must make base 6 and isolated area 4 is more than 10 μ m.In order to dwindle this distance A, once considered with reducing epitaxial loayer 5(3) electricalresistivity's's (raising impurity concentration) scheme.Promptly, by the depletion layer diffusion that suppresses to produce on base-collector junction and the collector electrode-isolation junction, just can decreased distance A, thereby just can dwindle the wiring pattern size in island district 5, in this case, the withstand voltage reduction of transistor that is directly proportional with depletion width, but for the integrated circuit that uses low-voltage, high withstand voltage because of not needing, therefore be out of question.
, when the electricalresistivity of epitaxial loayer 5 too reduces, can produce transistor magnification ratio h
FEThe inconsistent shortcoming of characteristic.And, owing to base 6, collector region 5 form positive-negative-positives with substrate 1 or isolated area 4, therefore there is the easily shortcoming of generation parasitic transistor effect.
Main purpose of the present invention is: do not influencing magnification ratio h
FESituation under, provide a kind of and can keep necessity and enough withstand voltage, can constitute and use bipolar transistor in the integrated circuit of low-voltage with the minimum wiring pattern dimension again.
Bipolar transistor of the present invention, has following formation: the 1st conductive-type semiconductor substrate, the 2nd conductive high concentration buried layer that on the surface layer part zone of Semiconductor substrate, forms, cover the 2nd conductivity type epitaxial loayer of whole surface of substrate and embedding buried layer, surround buried layer and connect the 1st conductive high concentration isolated area to Semiconductor substrate from epi-layer surface, surrounded by isolated area and be separated into the 2nd conductivity type collector region that epitaxial loayer constituted of island, the 1st conductivity type base that on the surface layer part zone of collector region, forms, the 1st zone of No. 2 electric type high concentration emitter region that on the surface layer part zone of base, forms and the 2nd conductive high concentration that on the surface of the collector region except that the base, forms, constitute by these, can dwindle the spacing distance of base and isolated area.
Fig. 1 represents in the integrated circuit longitudinal sectional drawing of bipolar transistor in the past.
Fig. 2 represents the longitudinal sectional drawing of the bipolar transistor in the integrated circuit of use low-voltage of the present invention.
Fig. 3 is the part enlarged drawing of Fig. 1, is used to illustrate that the present invention helps the effect of transistor miniaturization.
Fig. 4 represents the fragmentary cross-sectional view of the transistor arrangement of an alternative embodiment of the invention.
Fig. 5 represents the fragmentary cross-sectional view of the transistor arrangement of another embodiment of the present invention.
Fig. 6 is a transistorized vertical view shown in Figure 5.
Referring to Fig. 2, the figure shows the bipolar transistor longitudinal profile structure of one embodiment of the invention.On the surface layer part zone of P type semiconductor substrate 21, form N
+Type buried layer 22.In embedding this buried layer 22, form the epitaxial loayer 23 on the whole surface that covers Semiconductor substrate 21.Buried layer 22 is surrounds ground and be provided with from the surface of epitaxial loayer 23 and connect to the P of Semiconductor substrate 21
+Type isolated area 24.In the collector region 25 that is separated into island by isolated area 24, form transistor.Form P type base 26 on the surface layer part zone in collector region 25, form N on the surface layer part zone in base 26
+Type emitter region 27.In the superficial layer in collector region 25 on the All Ranges except that base 26, form N again
+The 1st zone 28 of type.Cover the surface of epitaxial loayers 23 with the such dielectric film of for example oxide-film 29,, collector electrode 40, base stage 41 and emitter 42 are contacted respectively with the 1st zone 28, base 26 and emitter region 27 as resistance by the electrode hole of this dielectric film 29.Like this, just constituted NPN transistor.
The electricalresistivity of epitaxial loayer 23 has and the same in the past value, and the 1st zone 28 diffuses to form simultaneously with emitter region 27.Collector electrode 40 is the contact zone with this 1st zone 28 and does the resistance contact.
Feature of the present invention is: the superficial layer of the collector region 25 except that base 26 is provided with N
+The 1st zone 28 of type.Use this structure neither to influence transistorized h
FEValue can be dwindled spacing A again.Its reason below is described.
Referring to Fig. 3, it amplifies the part details of Fig. 1.Owing to isolated area 24, base 26 and the 1st zone 28 all are that surface from epitaxial loayer 23 begins and the impurity thermal diffusion is formed, so these each regional border all is the such curved shape of diagram because of horizontal proliferation.Therefore, distance between the knot of base-collector junction and collector electrode-isolation junction is minimum range A in the surface, and along with knot portion deepens and increases gradually, and to the degree of depth place, bottom in the 1st zone 28, it is enough apart from B that spacing reaches.But because in the 1st zone 28 of high concentration, the depletion layer diffusion is suppressed in each knot portion, the depletion layer 35 that spreads along the knot face becomes zone as shown in phantom in FIG..
That is to say that in the surface of collector region 25, the 1st zone 28 has suppressed the diffusion of depletion layer 35, than the 1st zone 28 dark location, two knot faces are split up into enough distances.Therefore, distance A is just compared and can be dwindled with transistor in the past.But, if the 1st zone 28 is shallow excessively, just can not obtain enough apart from B.Therefore, must establish the degree of depth in the 1st zone 28 suitably.Also have, dwindle withstand voltage (V along with the width of depletion layer 35
CBO, C
C-SYB) will descend, therefore, must set the impurity concentration in the 1st zone 28, make its withstand voltage working voltage that is not less than.
The inventor forms the 1st zone 28 that identical diffusion depth and identical impurity concentration are arranged with emitter region 27 by satisfying these two conditions simultaneously with the emission diffusion technology, thereby has realized guaranteeing withstand voltage be 7V, the transistor of distance A≤5 μ m.But, the 1st zone 28 also not necessarily will form with emission diffusion technology process simultaneously.Much less, by using its impurity concentration of diffusion technology process control and diffusion depth separately, can set withstand voltage arbitrarily and distance A.
Use when of the present invention because of reducing the electricalresistivity of epitaxial loayer 23, so h can be provided
FEThe transistor of value high conformity.
Referring to Fig. 4, it shows the transistor of another embodiment of the present invention.The transistor of transistor AND gate Fig. 2 of this embodiment is similar, but different be that buried layer 22 forms must be more roomy than the bottom surface of the collector region 25 that is made of epitaxial loayer, and contact with isolated area 24.According to the transistor arrangement of this embodiment, by the charge carrier that emitter region 27 is injected, collector region 25 do not capture most charge carrier and can all be captured by buried layer 22, therefore, be the h of the PNP parasitic transistor of base stage with collector region 25
FEWill reduce.In addition, owing to expand buried layer 22 and make collector contact with the 1st zone 28, collector resistance rc reduces, thereby has just reduced the V of NPN transistor
CE(sat).That is to say, because the h of PNP parasitic transistor
FEReduce V with NPN transistor
CE(sat) reduce the effect that multiplies each other of these two factors, almost completely can prevent parasitic transistor effect.In this case, because buried layer 22 all is the joint of area with high mercury with engaging of isolated area 24, so withstand voltage (Vc-sub) decreases, be to be used on the integrated circuit that uses low-voltage because of transistor still, so be out of question.In addition, the transistorized manufacturing of this enforcement also can increase additivity diffusion technology process.
Fig. 5 has represented the transistor arrangement of another embodiment of the present invention.Also some is similar for the transistor of transistor AND gate Fig. 2 of this embodiment, but different is: be provided with from the surface in the epitaxial loayer on the boundary member of the collector region 25 that is made of epitaxial loayer and connect to the N of Semiconductor substrate 21
+The 2nd zone 30 of type high concentration.This 2nd zone 30 is arranged on the whole boundary member of collector region 25 shown in Fig. 6 vertical view, and according to the transistor arrangement of this embodiment, the 2nd zone 30 of high concentration can cause that collector resistance rc reduces, the V of NPN transistor
CE(SAT) reduce.Also have, that inject and captured not to the utmost charge carrier by emitter region 27 for collector region 25, can all be captured by the 2nd zone 30 and 22 of the buried layers of high concentration, therefore, collector region 25, be the h of the PNP parasitic transistor of base stage with 30
FEWill reduce.That is to say, because the h of PNP parasitic transistor
FEReduce V with NPN transistor
CE(sat) reduce the effect that multiplies each other of these two factors, almost completely can prevent this parasitic transistor effect.
The NPN transistor of this embodiment since the 1st zone 28 of high concentration suppress to play a part aspect the depletion layer diffusion the most basic, so withstand voltage (C of NPN transistor
CBO, V
C-sub) determined by the concentration in this 1st zone.So, the same with Fig. 1 embodiment situation, should not make withstand voltage be lower than working voltage when setting the impurity concentration in the 1st zone 28.
As mentioned above, use the present invention can use the integrated circuit miniaturization of low-voltage and highly integrated, and can provide and have non-parasitic transistor effect and the good bipolar transistor of characteristic.
Claims (4)
1, a kind of bipolar transistor, it comprises, the Semiconductor substrate of the 1st conductivity type, the high concentration buried layer of the 2nd conductivity type that on the surface layer part zone of above-mentioned substrate, forms, cover the epitaxial loayer of the 2nd conductivity type of the whole surface of above-mentioned substrate and embedding above-mentioned buried layer, surround above-mentioned buried layer and connect to the high concentration isolated area of the 1st conductivity type of substrate from the surface of above-mentioned epitaxial loayer, surrounded by above-mentioned isolated area and be separated into the collector region of the 2nd conductivity type island and that constitute by above-mentioned epitaxial loayer, the high concentration emitter region of the 2nd conductivity type that on the base of the 1st conductivity type that forms on the surface layer part zone of above-mentioned collector region and surface layer part zone, forms in above-mentioned base, on the superficial layer of above-mentioned collector region, connect the 1st zone of high concentration of the 2nd conductivity type on boundary with above-mentioned base and above-mentioned isolated area both sides, it is characterized in that the depletion layer amplitude on the PN junction in PN junction by suppressing to occur in above-mentioned base and the 1st district and above-mentioned isolated area and the 1st district, thereby the spacing distance of above-mentioned base and above-mentioned isolated area is dwindled.
2, bipolar transistor according to claim 1 is characterized in that above-mentioned buried layer is wideer than the bottom surface of the collector region that is made of above-mentioned epitaxial loayer, and contacts with above-mentioned isolated area, prevents parasitic transistor effect thus.
3, bipolar transistor according to claim 1, it is characterized in that the boundary member in the collector region that constitutes by above-mentioned epitaxial loayer, also have high concentration the 2nd zone, prevent parasitic transistor effect thus from above-mentioned epi-layer surface perforation to the 2nd conductivity type of above-mentioned substrate.
4, bipolar transistor according to claim 1 is characterized in that the 1st conductivity type is the P type, and the 2nd conductivity type is the N type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN86100558.9A CN1003334B (en) | 1985-04-19 | 1986-04-16 | Bipolar transistor |
Applications Claiming Priority (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60084829A JPS61242074A (en) | 1985-04-19 | 1985-04-19 | Transistor |
| JP84829/1985 | 1985-04-19 | ||
| JP10776585A JPS61280661A (en) | 1985-05-20 | 1985-05-20 | Transistor |
| JP107765/1985 | 1985-05-20 | ||
| JP107772/1985 | 1985-05-20 | ||
| JP10777285A JPS61280663A (en) | 1985-05-20 | 1985-05-20 | Transistor |
| CN86100558.9A CN1003334B (en) | 1985-04-19 | 1986-04-16 | Bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN86100558A CN86100558A (en) | 1986-10-15 |
| CN1003334B true CN1003334B (en) | 1989-02-15 |
Family
ID=27429924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN86100558.9A Expired CN1003334B (en) | 1985-04-19 | 1986-04-16 | Bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1003334B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4065104B2 (en) * | 2000-12-25 | 2008-03-19 | 三洋電機株式会社 | Semiconductor integrated circuit device and manufacturing method thereof |
| CN1315186C (en) * | 2004-05-01 | 2007-05-09 | 江苏长电科技股份有限公司 | Mini flipchip transistor and method for manufacturing same |
| US8581365B2 (en) * | 2011-04-22 | 2013-11-12 | Monolithic Power Systems, Inc. | Bipolar junction transistor with layout controlled base and associated methods of manufacturing |
| CN116153973A (en) * | 2023-04-18 | 2023-05-23 | 微龛(广州)半导体有限公司 | Vertical bipolar transistor and manufacturing method thereof |
-
1986
- 1986-04-16 CN CN86100558.9A patent/CN1003334B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CN86100558A (en) | 1986-10-15 |
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