JPH05121418A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the lowering of hFE by forming an oxidized film as a part of insulation film in a specified area through the CVD method. CONSTITUTION:A polycrystalline silicon layer 12a is arranged in such a way that it will be extended from a contact 11b and cover an epitaxial layer 4 between an insulation diffusion layer 5a and collector diffusion layer 9b. A CVD oxidized film 14 as an insulation film is not formed on an active area inside elements, and it merely covers the outer layer 12a. Since a CVD oxidized film 14 is not formed on the active area inside elements of L-PNP Tr. and V-PNP Tr., especially on the base layer, the generated charge does not accumulate, thereby permitting no centering of rejunction on the silicon surface and preventing the increase in base current. Thus, the characteristics of the device can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a transistor for a bipolar integrated circuit.

[0002]

2. Description of the Related Art First, regarding a high withstand voltage lateral PNP transistor of 40 V or more (hereinafter referred to as L-PNP Tr.) According to the prior art, a plan view of FIG.
A description will be given with reference to FIG. 3B which is a sectional view taken along the line C ′, and next, a conventional high breakdown voltage vertical PNP transistor of 40 V or more (hereinafter referred to as V-PNP Tr.) Will be described with reference to FIG.
FIG. 4 is a plan view of (a) and a sectional view taken along the line DD ′ of FIG.
This will be described with reference to (b).

The breakdown voltage of a bipolar transistor is generally guaranteed by the breakdown voltage between the emitter and collector (hereinafter referred to as BV _CEO ). To satisfy BV _CEO > 40V, first, LP
NPTr. The resistivity of the epitaxial layer 4 serving as the base layer is selected to be 3 to 5 Ω · cm and the thickness is 8 to 12 μm. Next, an L-PNPTr., Which is usually formed simultaneously with the high-concentration P-type external base (not shown) of the vertical NPN transistor. The conditions for the emitter 9a and the collector 9b of are determined. Since the junction has become shallower as the speed and integration of semiconductor integrated circuits have increased, for example, boron has been ion-implanted to reduce the junction depth 1 to 2.
It is formed in μm. To prevent punch-through, the emitter-collector distance, that is, the base width is 10 to 1
5 μm required. In order to reduce the reverse leakage current, the N-type diffusion 6 (including the emitter layer 9a) is used as a part of the base to reduce the grounded emitter current amplification factor (hereinafter referred to as h _FE ) by about 10 ¹⁶ cm ^-3 , depth about 3 ~
It is formed at 5 μm. In order to prevent electric field concentration on the surface of the collector-base junction, the inner and outer sides of the collector diffusion layer 9b are covered with aluminum wiring 15c serving as a collector electrode. Further, it is necessary to secure a P-type inversion voltage of 40 V or more on the surface of the N ⁻ type epitaxial layer 4 between the P ⁺ type collector diffusion layer 9b and the insulating diffusion layer 5a. Therefore, a polycrystalline silicon layer 12a having the same potential as the epitaxial layer is formed as a shield on the field oxide film 7 having a thickness of about 1 to 2 μm. Since the polycrystalline silicon layer 12a is made to have conductivity by ion-implanting arsenic, for example, an insulating film is required between the polycrystalline silicon layer 12a and the aluminum wirings 15a to 15c. As this insulating film, an oxide film 14 is formed by the CVD method to a thickness of about 3000 to 6000 angstroms. Conventionally, as shown in FIGS. 3 (a) and 3 (b), each of the contacts 11 of the emitter, the base, and the collector 11
The structure is such that the CVD oxide film 14 covers all of the layers a, 11b, and 11c except about 1 to 2 μm.

Similarly, the V-PNP Tr. Regarding also
As shown in FIGS. 4A and 4B, the emitter, the base,
Approximately 1-2 around the contacts 11a, 11b, 11c and 11d of the collector and the epitaxial layer, respectively.
Except for μm, the structure was covered with the CVD oxide film 14.

[0005]

[Problems to be Solved by the Invention] This conventional L-PNP
Tr. And V-PNP Tr. In the above, since the CVD oxide film 14 covers the entire surface of the transistor except the contact portions, a large amount of charges generated in the CVD oxide film 14 during aluminum sputtering or dry etching is accumulated. This accumulated charge induces a recombination center on the silicon surface immediately below. In particular, if there are many recombination centers on the surface of the epitaxial layer 4 serving as the base region, the recombination current on the surface causes an increase in the base current.
_In the graph of the dependence of _{FE on} the collector current I _C , there was a drawback that it caused a decrease in h _FE on the low current side.

[0006]

The semiconductor device of the present invention comprises:
A second-conductivity-type epitaxial layer is formed on one main surface of the first-conductivity-type semiconductor substrate, and the first-conductivity-type first region and the first region do not overlap with the first-conductivity-type first region on the epitaxial layer surface. A second conductive type region surrounding the first conductive type is formed, and an oxide film formed by a CVD method as a part of the insulating film is surrounded by at least the first region and the second region except the epitaxial layer. It is characterized by being formed on top.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS L-PNP T which is the first embodiment of the present invention.
r. FIG. 1A is a plan view and FIG.
A description will be given with reference to FIG. 1B which is a sectional view taken along line A ′.

An N ⁺ type buried layer 2 having a layer resistance of 20 to 50 Ω / □ and a P ⁺ type buried layer 3a having a layer resistance of 100 to 300 Ω / □ are formed on a P ⁻ type silicon substrate 1 having a specific resistance of 1 to 5 Ω · cm. ing. The N ⁺ type buried layer 2 is formed by diffusing antimony or arsenic, and is formed by the L-PNP Tr. As a part of the base of, the effect of suppressing the leakage of the emitter current and the collector current into the silicon substrate 1 is obtained. The P ⁺ type buried layer 3a is formed by diffusion of boron and ion implantation together with the P ⁺ type diffusion layer 5a and serves as an insulating separation band between adjacent elements. The N ⁻ type epitaxial layer 4 has a specific resistance of 3 to 5 Ω · cm and a thickness of 8 to 12
μm, L-PNP Tr. Constitutes the base layer of. The N-type diffusion layer 6 uses, for example, phosphorus with an acceleration energy 100
˜150 keV, dose amount 1 to 3 × 10 ¹³ cm ⁻² , formed by ion implantation, and constitutes a part of the base layer. P
^{The +} type diffusion layers 9a and 9b serve as an emitter and a collector, for example, for accelerating boron to an energy of 30 to 50 k.
eV, dose amount 1 to 3 × 10 ¹⁵ cm ⁻² are simultaneously formed by ion implantation. The emitter diffusion layer 9
a is completely contained in the N-type diffusion layer 6. As the insulating film, the field oxide film 7 having a thickness of 1 to 2 μm is the insulating separation band 3
A part of the epitaxial layer 4 on and inside a and 5a is formed. L-PNP Tr. A thermal oxide film 8 having a thickness of 500 to 1000 angstroms is formed on the active region of. 1000-200 thickness on the entire surface
It is covered with a 0 angstrom LPCVD nitride film 10. The polycrystalline silicon layer 1 is formed on the base contact 11b.
2a is formed, and arsenic is ion-implanted into this, and then annealed to obtain a surface concentration of 10 ²⁰ -1.
An N ⁺ type diffusion layer 13a having a depth of 0 ²¹ cm ^-3 and a depth of 1000 to 2000 angstrom is formed. The N ⁺ type diffusion layer 13a is usually formed simultaneously with the shallow emitter (not shown) of the vertical NPN transistor. Polycrystalline silicon layer 1
2a extends from the contact 11b, and the insulating diffusion layer 5a
Is disposed so as to cover the epitaxial layer 4 between the collector diffusion layer 9b and the collector diffusion layer 9b. The CVD oxide film 14 as an insulating film is not formed on the in-device active region, but only covers the outer polycrystalline silicon layer 12a. Emitter,
The collector electrodes are contacts 11a and 11c.
It is composed of aluminum wirings 15a and 15c via.
The base electrode is composed of aluminum wiring 15b via the polycrystalline silicon layer 12a. The emitter wiring 15a covers the outside of the emitter diffusion layer 9a, but does not extend to above the collector diffusion layer 9b. On the other hand, collector wiring 15
b covers both the inside and the outside of the collector diffusion layer 9b.

Next, a second embodiment of the present invention, VP
NP Tr. This will be described with reference to the plan view of FIG. 2A and FIG. 2B which is a cross-sectional view taken along the line BB ′ of FIG. The L-PNP Tr. The explanation of the part that overlaps with is omitted. The P ⁺ type buried layer 3b is formed at the same time as the insulating separation band 3a, and the V-PNP Tr. Which is a part of the collector of the N ⁺ type buried layer 2 and is completely contained in the silicon substrate 1.
And are floating. The P ⁺ type diffusion layer 5b is formed at the same time as the insulating separation band 5a, and the P ⁺ type buried layer 3b is formed.
It is linked to and is part of the collector. The inner epitaxial layer 4 and the N-type diffusion layer 6 surrounded by the P ⁺ -type diffusion layer 5b serve as a base, and the base contact layer 13a is shallowly formed with a high concentration through the polycrystalline silicon layer 12b. .. The P ⁺ type diffusion layer 9a forms an emitter layer. The polycrystalline silicon layer 12b forming the base contact layer 13a is formed only on the base contact 11b, and as a shield for preventing surface inversion, on the contact 11d connected to the epitaxial layer 4 outside the P ⁺ type diffusion layer 5b. Of the polycrystalline silicon layer 12a. CVD oxide film 1 as insulating film
4 is L-PNP Tr. Similar to the above, it is not formed on the active region in the element, but only covers the outer polycrystalline silicon layer 12a.

[0010]

As described above, according to the present invention, the CVD oxide film 14 is formed by the L-PNP Tr. And V-PNP T
r. Since it is not formed on the active region in the element, especially on the base layer, the generated charge is not accumulated, and therefore the recombination center is not induced on the silicon surface, and the increase of the base current can be prevented. Thus, as shown in FIG. 5, in the low current side h _FE
Can be eliminated, and the characteristics can be improved.

[Brief description of drawings]

FIG. 1A is an L-PN which is a first embodiment of the present invention.
P Tr. FIG. (B) is A- of (a)
It is an A'sectional view.

FIG. 2A is a V-PN which is a second embodiment of the present invention.
P Tr. FIG. (B) is B- of (a)
It is a B'sectional view.

FIG. 3 (a) shows a conventional L-PNP Tr. FIG. (B) is a CC 'sectional view of (a).

FIG. 4 (a) is a V-PNP Tr. FIG. (B) is a DD 'sectional view of (a).

FIG. 5 shows I _C dependence of h _FE of a transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P ⁻ type silicon substrate 2 N ⁺ type buried layer 3a, 3b P ⁺ type buried layer 4 N ⁻ type epitaxial layer 5a, 5b P ⁺ type diffusion layer 6 N type diffusion layer 9a, 9b P ⁺ type diffusion layer 13a , 13b N ⁺ type diffusion layer 7, 8, 14 Oxide film 10 Nitride film 11a-11d Contact 12a, 12b Polycrystalline silicon layer 15a-15d Aluminum wiring

Claims (1)

[Claims] 1. A second-conductivity-type epitaxial layer is formed on one main surface of a first-conductivity-type semiconductor substrate, and a first-conductivity-type conductive 1 region and the first region overlap each other on the surface of the epitaxial layer. And a second region of the first conductivity type that surrounds the first region, and an oxide film formed by a CVD method as a part of an insulating film is surrounded by at least the first region and the second region. A semiconductor device, which is formed on a surface other than the top.