JP2663751B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a lateral transistor for a bipolar integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a high breakdown voltage lateral PNP transistor of 50 V or more (hereinafter referred to as "L-PNP Tr").
5A will be described with reference to the plan view of FIG. 5A and FIG.

The breakdown voltage of a bipolar transistor is generally guaranteed by the breakdown voltage between the emitter and collector (hereinafter referred to as BV _CEO ).

In order to satisfy BV _CEO > 50 V, the L-PN
The specific resistance of the epitaxial layer 4 serving as the base layer of PTr is selected to be 3 to 5 Ω · cm, and the thickness is 9 to 13 μm. Next, the conditions of the emitter 10a and the collector 10b of the L-PNP Tr, which are formed simultaneously with the high-concentration P-type external base (not shown) of the vertical NPN transistor, are determined.

[0005] With the increase in speed and integration of semiconductor integrated circuits, the junction is becoming shallower. For example, boron is ion-implanted to form a junction depth of 1 to 2 μm.

In order to prevent punch-through, the emitter-collector distance, that is, the base width is required to be 10 to 15 μm.

[0007] To reduce the reverse leakage current by lowering the emitter ground current amplification factor (hereinafter referred to as h _FE), a surface concentration of about 10 ¹⁶ cm ^-3, a depth of about 3 to 5 N-type diffusion layer 7
Is formed as a part of the base (including the emitter layer 10a).

In order to prevent electric field concentration on the surface of the collector-base junction, the inside and outside of the collector diffusion layer 10b are covered with an aluminum wiring 13c serving as an emitter electrode.

In this way, as shown in the graph of the collector-emitter current-voltage characteristics in FIG. 4, BV _CEO ≒ 5
0 V is realized.

[0010]

In the conventional L-PNP transistor, BV _CEO ≒ 50 V, which has only a marginal capability, and it is necessary to further improve the design margin in view of manufacturing variations.

[0011] BV _CEO is the base-collector junction breakdown voltage and h
It is decided in consideration of _FE . 5A and 5B, the BV _CEO is determined by the collector diffusion layer 1.
This is a portion just below the emitter aluminum wiring 13a near the inner surface (emitter side) of Ob.

FIG. 3 shows a cross-sectional structure in which the vicinity of the collector is enlarged.
(A). BV _CEO is measured by applying a positive bias to the emitter 10a and a negative bias to the collector 10b. The positive electric field from the emitter wiring 12a is applied to the thermal oxide film 9 and the LPCV
This affects the underlying epitaxial layer 4 via the D nitride film 11. From the collector diffusion layer 10b to the epitaxial layer 4
The depletion layer 17 extending toward the surface shrinks near the surface, causing electric field concentration. Since the current path is determined inside near the emitter, h
_{The FE} multiplication determines the BV _CEO .

[0013]

According to the present invention, there is provided a semiconductor device comprising:
An epitaxial layer of one conductivity type is formed on one main surface of the semiconductor substrate, and a first region of the opposite conductivity type and a second region of the opposite conductivity type surrounding the first region without overlapping the first region on the surface of the epitaxial layer. Is formed on the first region and the second region, a lower metal wiring connected to each is formed, an interlayer insulating film covering the lower metal wiring is formed, and an opening formed in the interlayer insulating film is formed. Through the first
An upper layer wiring connected to the lower layer wiring in the region is formed, and the upper layer wiring constitutes a lead electrode crossing over the second region.

[0014]

[0015]

FIG. 1 (a) shows a first embodiment of the present invention.
Will be described with reference to FIG. 1B, which is a plan view of FIG.

An N ⁺ type buried layer 2 having a layer resistance of 20 to 50 Ω / □ and a P ⁺ type buried layer 3 having a layer resistance of 100 to 300 Ω / □ are formed on a P ⁻ type silicon substrate 1 having a specific resistance of 1 to 5 Ω · cm. ing.

The N ⁺ type buried layer 2 is formed by diffusing antimony or arsenic, and has an effect of suppressing leakage of an emitter current and a collector current to the P ⁻ type silicon substrate 1 as a part of the base of the L-PNP Tr. There is.

The P ⁺ -type buried layer 3 is formed together with the P ⁺ -type diffusion layer 5 by boron diffusion or ion implantation, and serves as an insulating separator between adjacent elements.

The N ⁻ type epitaxial layer 4 has a specific resistance of 3 to 5
Ω · cm, 9 to 13 μm in thickness, constitutes a base layer of L-PNP Tr.

The layer resistance is 10 to 3 as a base contact layer.
The N ⁺ -type diffusion layer 6 of 0Ω / □ is formed by, for example, phosphorus diffusion.

The N-type diffusion layer 7 is made of, for example, phosphorous with an acceleration energy of 100 to 150 keV and a dose (dose) of 1 to 2 × 10
It is formed by ion implantation at ¹³ cm ^-2 and constitutes a part of the base layer.

The P ⁺ -type diffusion layers 10a and 10b serve as an emitter and a collector, respectively. For example, boron is supplied with an acceleration energy of 30 to 50 keV and a dose (dose) of 1 to 2 × 1.
It is simultaneously formed by ion implantation at 0 ¹⁵ cm ^-2 .

The emitter diffusion layer 10a is completely contained in the N-type diffusion layer 7.

As an insulating film, a thick field oxide film 8 having a thickness of 1 to 2 μm is formed on insulating separation zones 3 and 5.
On the other hand, on the L-PNP Tr, a thickness of 500 to 1000 A
A thin thermal oxide film 9 is formed. 100 thickness all over
The LPCVD nitride film 11 of 0 to 2000 A covers.

The electrodes of the emitter, base and collector of the L-PNP Tr have openings 12a, 12b and 12c, respectively.
Through the lower aluminum wirings 13a, 13b, 13c.

The emitter wiring 13a is connected to the emitter diffusion layer 10
a, but does not extend over the collector diffusion layer 10b. On the other hand, the collector wiring 13c covers both inside and outside of the collector diffusion layer 10b.

The nitride film 14 having a thickness of 1 μm formed by plasma CVD is an interlayer insulating film. Emitter wiring 1
A through hole 15 is opened in the nitride film 14 on 3a,
From here, it is connected to the upper aluminum wiring 16 to form an emitter extraction electrode.

FIG. 3 is an enlarged sectional view showing the vicinity of the collector of this embodiment.
(B). The positive electric field from the emitter wiring 16 is weakened by the interlayer nitride film 14. Furthermore, collector wiring 1 of negative electric field
Reference numeral 3c widely covers the collector diffusion layer 10b as a lower aluminum wiring. The depletion layer 17 can extend to near the surface, so that the electric field concentration is reduced.

[0029] Therefore, as shown in FIG. 4, BV _CEO ≒
65 V can be realized, and BV _CEO > 50 V can be satisfied with a margin.

FIG. 2 shows a second embodiment of the present invention.
FIG. 2 which is a plan view of FIG.
This will be described with reference to FIG.

In this embodiment, a part of the collector diffusion layer 10b is removed. The emitter wiring 13a is drawn out through the removed portion. Therefore, the through hole 15 and the upper aluminum wiring 16 as in the first embodiment are unnecessary.

In the second embodiment, since the collector diffusion layer 10b under the emitter wiring 13a was removed, as shown in FIG. 4, the breakdown voltage was further improved and BV _CEO ≒ 65 V was obtained.

[0033]

The effect of the electric field on the underlying substrate can be reduced by isolating the extraction electrode of the emitter from the collector diffusion layer. As a result, the collector breakdown voltage BV _CEO could be improved to 65 to 70V.

[Brief description of the drawings]

FIG. 1A is a plan view showing a first embodiment of the present invention. (B) is AB sectional drawing of (a).

FIG. 2A is a plan view showing a second embodiment of the present invention. (B) is AB sectional drawing of (a).

FIG. 3A is an enlarged cross-sectional view near a collector of a conventional lateral PNP transistor. FIG. 2B is an enlarged sectional view near the collector according to the first embodiment of the present invention.

FIG. 4 is a graph showing a reverse bias current-voltage characteristic between an emitter and a collector.

FIG. 5A is a plan view of a conventional lateral PNP transistor. (B) is AB sectional drawing of (a).

[Explanation of symbols]

1 P ^- -type silicon substrate 2 N ⁺ -type buried layer 3 P ⁺ -type buried layer 4 N ^- -type epitaxial layer 5 P ⁺ -type diffusion layer 6 N ⁺ -type diffusion layer 7 N-type diffusion layer 8 field oxide film 9 oxide film 10a, 10b P ⁺ type diffusion layer 11 nitride film 12a, 12b, 12c contact 13a, 13b, 13c aluminum wiring 14 nitride film 15 through hole 16 aluminum wiring 17 depletion layer

Claims (1)

(57) [Claims] An epitaxial layer of one conductivity type is formed on one main surface of a semiconductor substrate, and a first region of a reverse conductivity type and a reverse conductivity surrounding the first region without overlapping the first region on the surface of the epitaxial layer. A mold second region, a lower metal interconnection connected to each of the first and second regions is formed, an interlayer insulating film covering the lower metal interconnection is formed, and the interlayer insulating film is formed. A semiconductor device in which an upper layer wiring connected to the lower layer wiring in the first region is formed through an opening formed in the first region, and a lead electrode crossing over the second region by the upper layer wiring.