JPS62163341A - Patterning method for high melting-point metallic film - Google Patents

Patterning method for high melting-point metallic film

Info

Publication number
JPS62163341A
JPS62163341A JP526686A JP526686A JPS62163341A JP S62163341 A JPS62163341 A JP S62163341A JP 526686 A JP526686 A JP 526686A JP 526686 A JP526686 A JP 526686A JP S62163341 A JPS62163341 A JP S62163341A
Authority
JP
Japan
Prior art keywords
film
high melting
mask
sog
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP526686A
Other languages
Japanese (ja)
Inventor
Fumihiko Inoue
文彦 井上
Hiroshi Goto
寛 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP526686A priority Critical patent/JPS62163341A/en
Publication of JPS62163341A publication Critical patent/JPS62163341A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To use a high melting-point metal as a material for an electrode or a wiring layer, and to improve the characteristics of an integrated circuit by a method wherein two layers of an SOG film and a nitride film are laminated on a high melting-point metallic film, an opening section is formed to the nitride film through dry etching, employing a resist film as a mask, the resist film is removed through wet treatment and said SOG film and the high melting- point metallic film are each dry-etched, using the nitride film as a mask. CONSTITUTION:An element isolation region and a gate oxide film 2, etc. are shaped to an silicon substrate 1, and a high melting-point metallic film 3 consisting of Mo, W, Ti, etc. is laminated through a sputtering method. The solution of SOG (Spin On Glass) is applied and dried, and a nitride film 5 is laminated. A resist film 6 is applied. An opening section is formed to the nitride film 5 through plasma-etching, using a resist film as a mask. The resist film 6 is removed through a wet treatment method by an oxidizing strong acid. An SOG film 4 is bored through plasma-etching, employing the nitride film 5 bored through said processes as a mask, and an atmosphere is changed over to CCl4 gas and the high melting-point metallic film 3 is etched.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の集積度か向上し高速性が要求されるに伴っ
て、配線層に用いる導電材料としては高融点材料で且つ
低抵抗特性が要求されている。この要求に適合するMo
、W、Ti等の材料を直接パターンニングした後、レジ
ストをウェット処理にて酸化性強酸で除去すると、高融
点金属の溶解の問題があり、この問題の解決を図った。
DETAILED DESCRIPTION OF THE INVENTION [Summary] As the degree of integration of semiconductor devices increases and high speed performance is required, conductive materials used in wiring layers are required to have high melting point materials and low resistance characteristics. Mo that meets this requirement
, W, Ti, etc., and then removing the resist with a strong oxidizing acid in a wet process, there is a problem that the high melting point metal dissolves, and this problem was solved.

〔産業上の利用分野〕[Industrial application field]

本発明は、高融点金属のパターンニング方法に関する。 The present invention relates to a method for patterning a refractory metal.

半導体装置の電極あるいは配線層の材料としては、古く
よりアルミニウムとか多結晶シリコンが専ら使用されて
いる。
Aluminum and polycrystalline silicon have long been used as materials for electrodes or wiring layers in semiconductor devices.

アルミニウムは、金属膜として形成した後、その後工程
で高温処理を含む場合は使用困難であり、また多結晶シ
リコンは高速性を要求される場合、その抵抗値の更に低
い金属材料が求められる。
Aluminum is difficult to use if high-temperature treatment is involved in subsequent steps after it is formed as a metal film, and polycrystalline silicon is required to have a metal material with even lower resistance when high-speed performance is required.

後者の問題に対しては、高融点金属のシリサ・イド(W
Si2.MoSi2.Ti5iz等)が多結晶シリコン
よりも抵抗値が一桁小さいのでMOS F ETのゲー
ト電極材料として使用されている。
To solve the latter problem, high melting point metal silicide (W
Si2. MoSi2. Ti5iz, etc.) is used as a gate electrode material for MOS FETs because its resistance value is one order of magnitude lower than that of polycrystalline silicon.

更に、ンリサイド合金よりも一桁抵抗値の小さい高融点
金属を、重体として使用することが望まれるが、パター
ンニング時に問題があり改善が要望されている。
Further, it is desired to use a high melting point metal having a resistance value one order of magnitude lower than that of the silicide alloy as the heavy body, but there are problems during patterning, and improvements are desired.

〔従来の技術〕[Conventional technology]

現在のアルミニウム、多結晶シリコン、シリサ・イド合
金等の材料は金属膜として実用化しているが、高融点金
属材料を直接電極、配線層に使用するプロセスについて
は未だ開発段階にある。
Current materials such as aluminum, polycrystalline silicon, and silicide alloys have been put into practical use as metal films, but processes that use high-melting point metal materials directly for electrodes and wiring layers are still in the development stage.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

高融点金属膜を積層するのは、CVD法あるいはスパッ
クリング法等で積層される。
The high melting point metal films are laminated by a CVD method, a spackling method, or the like.

積層された高融点金属膜をフォトリソグラフィ手法を用
い、レジスト膜のパターンニングを行って、これをマス
クとして高融点金属膜をエツチングを行ったとする。
Assume that the laminated high melting point metal film is patterned into a resist film using a photolithography method, and the high melting point metal film is etched using this as a mask.

エツチング終了後、レジスト膜を剥離することか必要で
あるが、これを通常のウェット処理で行うと高融点金属
材料が処理液に溶解するという問題を生ずる。
After the etching is completed, it is necessary to peel off the resist film, but if this is done by normal wet processing, a problem arises in that the high melting point metal material dissolves in the processing solution.

レジストの!I(1離溶液としては、加2さされた過酸
化水素水に濃硫酸を加えた酸化性強酸を使用するが、こ
の溶液は高融点金属とも反応してレジストと共に高融点
金属の溶解現象を起こす。
Resist! I (1) As a syneresis solution, a strong oxidizing acid prepared by adding concentrated sulfuric acid to hydrogen peroxide solution is used, but this solution also reacts with high melting point metals and causes the dissolution phenomenon of high melting point metals together with the resist. wake up

レジストの剥離には、ウェット法以外にドライ法として
酸素プラスマによるアッシング法も多く用いられている
が、高融点金属膜の酸化の問題があり、また量産性を考
えるとウェット法の長所も捨てがたい。
In addition to the wet method, an ashing method using oxygen plasma is often used as a dry method for resist stripping, but there is a problem with the oxidation of the high-melting point metal film, and the advantages of the wet method may not be sacrificed in terms of mass production. sea bream.

高融点金属膜を形成後、その表面は絶縁膜で被覆するこ
とが要求されるので、本発明では絶縁膜をマスクとして
高融点金属膜のパターンニングを行って、絶縁膜のマス
クは除去せずに、そのまま使用する方法で改善を行った
After the high melting point metal film is formed, its surface is required to be covered with an insulating film, so in the present invention, the high melting point metal film is patterned using the insulating film as a mask, without removing the mask of the insulating film. We made improvements by using the method as is.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は、高融点金属膜上にSOG膜、次いで窒化
膜の2層を積層した後、レジスト除去を塗布、バクーン
ニング後、該レジスト膜をマスクとして、ドライエツチ
ングにより前記窒化膜に開口部を形成する。
The above problem can be solved by laminating two layers, an SOG film and then a nitride film, on a high melting point metal film, applying a resist remover, baking, and using the resist film as a mask, dry etching to create an opening in the nitride film. form.

次いで、前記レジスト膜をウェット処理により除去した
後、前記開口部を形成せる窒化膜をマスクとして、前記
SOG膜及び高融点金属膜をそれぞれドライエツチング
して高融点金属膜のパターンニングを行う本発明の高融
点金属膜のパターンニング法によって解決される。
Next, after the resist film is removed by wet processing, the SOG film and the high melting point metal film are each dry etched using the nitride film forming the opening as a mask to pattern the high melting point metal film. This problem is solved by the patterning method of refractory metal film.

〔作用〕[Effect]

レジスト除去のウェット処理工程では、高融点金属膜は
SOG膜かあるいはSOG膜と窒化膜の二重膜に覆われ
ているので、直接に酸化性強酸に曝されることはない。
In the wet process for removing the resist, the high melting point metal film is covered with the SOG film or the double film of the SOG film and the nitride film, so it is not directly exposed to strong oxidizing acid.

また、パターンニングされて残された高融点金属膜は、
SOG膜と窒化膜の二重絶縁膜に覆われているが、これ
はそのまま装置の絶縁膜として使用することが出来る。
In addition, the high melting point metal film left after patterning is
Although it is covered with a double insulating film of an SOG film and a nitride film, this can be used as it is as an insulating film for the device.

〔実施例〕〔Example〕

本発明による一実施例を図面により詳細説明する。 An embodiment according to the present invention will be described in detail with reference to the drawings.

MOSFETを形成するとして、シリコン基板1には既
に素子分離領域とゲート酸化膜2等は通常の方法で形成
されているとする。図面では直接本発明に関係のない部
分は省略する。
Assume that when a MOSFET is to be formed, an element isolation region, a gate oxide film 2, etc. have already been formed on a silicon substrate 1 by a normal method. In the drawings, parts not directly related to the present invention are omitted.

次いで、Mo、W、Ti等の高融点金属膜3をスパック
リング法で積層する。高融点金属膜は後にゲート電極と
配線層となるが、従来の多結晶シリコンを用いる場合に
比して、抵抗値が著しく小さいので膜厚は薄くで済む。
Next, a high melting point metal film 3 such as Mo, W, Ti, etc. is laminated by a spuckling method. The high melting point metal film will later become a gate electrode and a wiring layer, but since it has a significantly lower resistance value than when conventional polycrystalline silicon is used, the film can be made thinner.

次いで、SOG (Spin On Glass)の?
容、夜を塗布して乾燥させる。SOG膜4の厚さは80
0〜1000人とする。更に、窒化膜5を気相成長法で
約1000人積層する。次いで、レジスト膜6を塗布す
る。これを第1図に示す。
Next, SOG (Spin On Glass)?
Apply the mixture at night and let it dry. The thickness of the SOG film 4 is 80
0 to 1000 people. Further, about 1000 layers of nitride film 5 are deposited by vapor phase growth. Next, a resist film 6 is applied. This is shown in FIG.

上記レジスト膜6をパターンニングし、ゲート電極領域
を残す。
The resist film 6 is patterned to leave a gate electrode region.

次いで、上記レジスト膜をマスクとして、CF4+0□
ガスを導入せるプラズマ・エツチングにより窒化膜5に
開口部を形成する。これを第2図に示す。
Next, using the above resist film as a mask, CF4+0□
An opening is formed in the nitride film 5 by plasma etching that introduces gas. This is shown in FIG.

次いで、酸化性強酸によるウェット処理法によりレジス
ト膜6を除去する。上記処理ではSOG膜4あるいは窒
化膜5が溶解するごとはない。
Next, the resist film 6 is removed by wet processing using a strong oxidizing acid. In the above treatment, the SOG film 4 or the nitride film 5 never dissolves.

前記工程で開口された窒化膜5をマスクとしてCHF3
ガスを用いて、プラズマ・エツチングによりSOG膜4
を開口し、さらにCCl4ガスに切り換えて高融点金属
膜3のエツチングを行って、第3図が得られる。
Using the nitride film 5 opened in the above process as a mask, CHF3 is
The SOG film 4 is formed by plasma etching using gas.
Then, the high melting point metal film 3 is etched by switching to CCl4 gas to obtain the image shown in FIG.

上記のプロセスにより、SOG膜と窒化膜に積層された
高融点金属膜のパターンが得られ、高融点金属膜に積層
されたSOG膜と窒化膜は、そのまま使用することが可
能である。
Through the above process, a pattern of a high melting point metal film laminated on an SOG film and a nitride film is obtained, and the SOG film and nitride film laminated on a high melting point metal film can be used as they are.

〔発明の効果〕〔Effect of the invention〕

以上に説明せるごとく、本発明のパターンニング法を適
用することにより、高融点金属を電極あるいは配線層の
材料として用いることが可能となり、集積回路の特性の
向」二に寄与すること大である。
As explained above, by applying the patterning method of the present invention, it becomes possible to use high-melting point metals as materials for electrodes or wiring layers, which greatly contributes to improving the characteristics of integrated circuits. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図は本発明にかかわる高融点金、7膜のパ
ターンニング法を工程順に断面図で示す。 図面において、 1はシリコン基板、 2はゲート酸化膜、 3は高融点金属膜、 4はSOG膜、 5は窒化膜、 6はレジスト膜、 をそれぞれ示す。
FIGS. 1 to 3 are cross-sectional views showing the patterning method for seven films of high melting point gold according to the present invention in the order of steps. In the drawings, 1 is a silicon substrate, 2 is a gate oxide film, 3 is a high melting point metal film, 4 is an SOG film, 5 is a nitride film, and 6 is a resist film.

Claims (1)

【特許請求の範囲】 高融点金属膜(3)上にSOG膜(4)、次いで窒化膜
(5)の2層を積層した後、 レジスト膜(6)を塗布、パターンニング後、該レジス
ト膜をマスクとして、ドライエッチングにより前記窒化
膜(5)に開口部を形成する工程と、前記レジスト膜を
ウェット処理により除去した後、前記開口部を形成せる
窒化膜をマスクとして、前記SOG膜(4)及び高融点
金属膜(3)をそれぞれドライエッチングする工程を含
むことを特徴とする高融点金属膜のパターンニング法。
[Claims] After laminating two layers of an SOG film (4) and then a nitride film (5) on a high melting point metal film (3), a resist film (6) is applied and patterned, and then the resist film A step of forming an opening in the nitride film (5) by dry etching using the mask as a mask, and removing the resist film by wet processing. ) and the refractory metal film (3), each of which is dry etched.
JP526686A 1986-01-14 1986-01-14 Patterning method for high melting-point metallic film Pending JPS62163341A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP526686A JPS62163341A (en) 1986-01-14 1986-01-14 Patterning method for high melting-point metallic film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP526686A JPS62163341A (en) 1986-01-14 1986-01-14 Patterning method for high melting-point metallic film

Publications (1)

Publication Number Publication Date
JPS62163341A true JPS62163341A (en) 1987-07-20

Family

ID=11606425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP526686A Pending JPS62163341A (en) 1986-01-14 1986-01-14 Patterning method for high melting-point metallic film

Country Status (1)

Country Link
JP (1) JPS62163341A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186120A (en) * 1994-12-28 1996-07-16 Nec Corp Manufacture of semiconductor device
US5581126A (en) * 1995-09-14 1996-12-03 Advanced Micro Devices, Inc. Interlaced layout configuration for differential pairs of interconnect lines
KR100364810B1 (en) * 2000-02-22 2002-12-16 주식회사 하이닉스반도체 Method for fabricating of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186120A (en) * 1994-12-28 1996-07-16 Nec Corp Manufacture of semiconductor device
US5581126A (en) * 1995-09-14 1996-12-03 Advanced Micro Devices, Inc. Interlaced layout configuration for differential pairs of interconnect lines
KR100364810B1 (en) * 2000-02-22 2002-12-16 주식회사 하이닉스반도체 Method for fabricating of semiconductor device

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