JPS62163130A - Working speed controller for microcomputer - Google Patents

Abstract

PURPOSE:To increase the overall processing speed of a system by changing the frequency division ratio of a variable frequency dividing circuit and then switching the dividing clock signals applied to a microcomputer to switch the working speed of the microcomputer. CONSTITUTION:The clock signal outputted from a clock generating circuit 1 is supplied to a variable frequency dividing circuit 12 via a clock signal line 2. Then the clock signals frequency-divided properly are applied to a microcomputer 3 via a frequency divided clock signal line 13. The computer 3 issues the address data to an address decoder 5 via an address bus 4 at a specified speed. While plural IC devices 6-8 are connected to the decoder 5 via chip selection signal lines 9-11. Thus the computer 3 works at a speed in response to the working speed of a selected IC device. In such a way, the overall processing speed of a system is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to a microcomputer system equipped with a plurality of IC devices having different operating speeds.
The present invention relates to an operating speed control device for a microcomputer that switches the operating speed of a microcomputer according to the operating speed of the device to increase the processing speed of the entire system.

(Prior Art) FIG. 2 shows a block circuit diagram of a conventional microcomputer system. In FIG. 2, clock generation circuit 1
A clock signal output from the microcomputer 3 is given to the microcomputer 3 via a clock signal line 2. This microcomputer 3 supplies address data to an address decoder 5 via an address bus 4 at an operating speed according to a clock signal. Then, the address decoder 5 has a plurality of I
C devices 6, 7.8 each have a chip select signal line 9.
10. Connected via I+, selectively controls any one of the plurality of IC devices 6, 7.8 according to address data output from the microcomputer 3, and writes or writes data to the selected IC device. Data is read from the IC device and processed appropriately by the microcomputer 3.

(Problems to be Solved by the Invention) By the way, the operating speeds of the IC devices 6, 7, and 8 are various, and if the operating speed of the microcomputer 3 is too fast for the IC device with a slow operating speed, the IC device cannot write or read proper data. Therefore, the operating speed of the microcomputer 3 is determined according to the IC device with the slowest operating speed.
There was a problem in that the processing speed of the entire system was slow due to the inclusion of devices. Note that in order to increase the processing speed of the entire system, it is desirable that all the multiple IC devices have the same high operating speed, but generally speaking, IC devices with faster operating speeds are more expensive. This poses a problem in that the entire system becomes expensive.

An object of the present invention was to solve the problems of the conventional microcomputer system described above, and by switching the operating speed of the microcomputer according to the operating speed of the selected IC device, the system as a whole can process An object of the present invention is to provide a microcomputer operating speed control device that increases the speed.

(Steps to Solve the Problems) In order to achieve the above object, the microcomputer operating speed control device of the present invention includes a clock generation circuit that generates a clock signal, a microcomputer, and a clock signal that separates the clock signal. a variable frequency divider circuit that outputs a frequency-divided clock signal to the microcomputer, a plurality of IC devices having different operating speeds, and one of the plurality of IC devices according to address data output from the microcomputer. an address decoder for selectively controlling an IC selected by the address decoder;
The frequency dividing ratio of the variable frequency dividing circuit is configured to be changed depending on the operating speed of the device.

(Function) The operating speed of the microcomputer is changed by changing the dividing ratio of the variable frequency dividing circuit according to the operating speed of the selected IC device and switching the divided clock signal given to the microcomputer. , even if IC devices with different operating speeds are included, ICs with slower operating speeds
When a device is selected, the microcomputer operates at a similar speed, and when an IC device with a high operating speed is selected, the microcomputer also operates at a fast speed, making it possible to increase the processing speed of the entire system.

(Description of Examples) Hereinafter, examples of the present invention will be described with reference to FIG. FIG. 1 is a block circuit diagram of a microcomputer system incorporating an embodiment of the microcomputer operating speed control device of the present invention.

In FIG. 1, a clock signal output from a clock generation circuit 1 is given to a variable frequency divider circuit 12 via a clock signal line 2, and a frequency-divided clock signal whose frequency is appropriately divided is sent to a frequency-divided clock signal line 13. It is given to the microcomputer 3 via. This microcomputer 3 sends address data to an address decoder 5 via an address bus 4 at an operating speed determined by a divided clock signal.
I can do it.

The address decoder 5 includes a plurality of IC devices 6.7.
8 are connected via chip select signal lines 9, 10 and 11, respectively. Here, it is assumed that one IC device 6 has a different operating speed and is slower than the other IC devices 7.8. Therefore, the depth select signal line 9 of the IC device 6, which operates at a slow speed, is connected to the variable frequency dividing circuit 12. The address decoder 5 selectively controls one of the IC devices 6, 7.8 according to the address data output from the microcomputer 3. When the IC device 6 is selected, the address decoder 5 controls the variable frequency dividing circuit 12. A chip select signal is given,
The frequency division ratio of the variable frequency divider circuit 12 is increased, the frequency of the divided clock signal is lowered, and the operation speed of the microcomputer 3 is switched to become slower. When the IC device 7.8 with a fast operating speed is selected, no chip select signal is applied to the variable frequency divider circuit 12, the frequency division ratio is small, and the operating speed of the microcomputer 3 is fast.

Therefore, the microcomputer 3 selects the selected I
The microcomputer operates at a speed corresponding to the operating speed of the IC device, and the processing speed of the entire system can be increased compared to the conventional microcomputer in which the microcomputer always operates at the operating speed of the slowest IC device. Moreover, according to the operating speed control device of the present invention, since the operating speed is switched by hardware, no burden is placed on the program of the microcomputer 3. Furthermore, even if an IC device with a slow operating speed is incorporated into a system together with other IC devices with a fast operating speed, the fast operating speed of the other IC devices will not be impaired.

In addition, in the second embodiment, the IC device has two speeds, a slow operation speed and a fast operation speed. However, the IC device is not limited to this, and as long as the IC device has two or more speeds, the IC device can operate at two speeds. The frequency dividing ratio of the variable frequency dividing circuit 12 may be changed in two or more stages according to the operating speed, so that the microcomputer 3 can be switched to two or more operating speeds.

(Effects of the Invention) As explained above, according to the operating speed control device for a microcomputer of the present invention, the frequency dividing ratio of the variable frequency dividing circuit is changed according to the operating speed of the selected IC device. The operating speed of the microcomputer is changed by switching the frequency-divided clock signal that is applied, so even if IC devices with different operating speeds are included, when an IC device with a slower operating speed is selected, the microcomputer When an IC device with a high operating speed is selected, the microcomputer also operates at a fast speed, and the processing speed of the entire system can be increased, which is an excellent effect.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of a microcomputer system incorporating an embodiment of the microcomputer operating speed control device of the present invention, and FIG. 2 is a block circuit diagram of a conventional microcomputer system. 1: Clock generation circuit, 3: Microcomputer, 5 Near address decoder, 6.7.8: IC device, 12: Variable frequency dividing circuit. Figure 1

Claims (1)

[Claims] a clock generation circuit that generates a clock signal, a microcomputer, a variable frequency divider circuit that outputs a frequency-divided clock signal obtained by dividing the clock signal to the microcomputer, a plurality of IC devices having different operating speeds, and the microcomputer. an address decoder that selectively controls any one of the plurality of IC devices using address data output from a computer, and the variable frequency division according to the operating speed of the IC device selected by the address decoder. An operating speed control device for a microcomputer, characterized in that the frequency division ratio of the circuit is changed.