JPH09212479A - Single-chip microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it easy to design a layout and to increase the degree of freedom of modules by placing a CPU and peripheral modules in operation with independent clocks and making them interact on a handshake basis. SOLUTION: The CPU 5 and peripheral modules 1-4 operate with the independent clocks ϕ0, and ϕ1-ϕ4. The clocks ϕ0-ϕ4 are generated by clock generators 6, and 14-17. Acknowledgement signals 18 for handshake interaction are outputted by all the peripheral modules, pulled up to Vcc and then wired- ORed, and inputted to the CPU module 5. Therefore, the CPU 5 and peripheral modules can operate with the independent clocks ϕ0-ϕ4, so maximum performance can be derived and inter-module interfacing is asynchronous, so the respective modules can easily be connected. Further, the performance of the whole microcomputer is affected little by the layout design of clock wiring, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single chip microcomputer.

[0002]

2. Description of the Related Art An example of the prior art is shown in FIGS.

In addition to the CPU module 5 and the clock generator 6, a single-chip microcomputer (microcomputer) has a ROM 7, a RAM 8, a plurality of peripheral modules 1, 2, 3, 4 and a port 9 mounted on one chip. .

ROM7 of modules other than CPU5,
The RAM 8, the peripheral modules 1, 2, 3, 4 and the port 9 are uniquely assigned to the addresses, and the CPU is
Specify the address to access the corresponding module. The CPU outputs the address to the address bus 10. For read access, read signal 12
When performing write access, the CPU outputs the write signal 13 respectively. The read or write data is output to the data bus 11 and taken into the corresponding module. These series of operations are executed according to the program stored in the ROM.

The system clock φ is generated by the clock generator 6 and supplied to each module. The microcomputer operates according to this system clock φ. That is, all the modules on the chip are operating in synchronization.

On the other hand, the miniaturization of the LSI technology has progressed, and the microcomputers have become faster and more diversified in function due to the demands of the times.

Therefore, the generations of the microcomputers are changed, and the processing speed and the operation clock speed are increasing. However, it is impossible to develop all conventional assets, especially various peripheral modules in a short period of time, and it is possible to connect with existing peripheral modules. FIG. 2 is an example of an operation sequence of the single chip microcomputer. Although the basic bus cycle is 2 clocks, the old module operating in 1 cycle and 3 clocks can be accessed. This is dealt with by including in the CPU 5 logic for judging which module is to be accessed.

From the above, the problems in the prior art are
It is summarized below.

1) A logic for determining the type of module is required in the CPU, and therefore, a logic change is required every time the mounted peripheral module is changed.

2) Since the modules in the chip operate in synchronization with the same clock, the performance of the microcomputer is limited by the module with the slowest speed.

3) Due to the diversification of functions, when many modules are mounted, the chip size becomes large, the clock wiring becomes long, and the clock delay amount to the module of the terminal becomes large. Since the modules in the chip operate in synchronization with the same clock, the performance of the microcomputer is affected by the layout design of the clock wiring and the like.

4) When a peripheral module that operates at a higher speed than the CPU is mounted, it is necessary to synchronize the interface units, which may limit the performance of each.

[0013]

As described above, in the conventional single-chip microcomputer, 1) it is necessary to change the logic of the CPU every time the peripheral module is changed.

2) The module with the slowest speed determines the speed of the entire microcomputer.

3) When many peripheral modules are mounted, the speed of the entire microcomputer is easily affected by the layout design.

4) It is difficult to mount a peripheral module that operates faster than the CPU.

There is a problem.

[0018]

In the conventional single-chip microcomputer, all the modules in the chip operate with the same clock, and the CPU module and each module operate in synchronization.

Here, the bus interface timing in the chip is made asynchronous, that is, the modules are handshaked with each other, and a clock generator is provided for each module so that each module can operate at a different speed clock. Provided.

According to the above means, since the CPU and the peripheral modules can operate with independent clocks, the maximum performance can be obtained, and since the inter-module interface is asynchronous (operates by handshake), each module is connected. Will be easier. Further, the performance of the entire microcomputer can be made less susceptible to the layout design of the clock wiring and the like.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. 3, 4, 5 and 6.

In FIG. 3, the CPU 5 and each of the peripheral modules 1, 2, 3, 4 have independent clocks φ0, φ1, φ.
It is operating at 2, φ3 and φ4. φ0, φ1, φ2, φ
3 and φ4 are clock generators 6 and 1 respectively.
It is generated by 4, 15, 16, 17.

The acknowledge signal 18, which is exchanged by handshake, is output from all the peripheral modules and wired-ORed by pulling up to Vcc and input to the CPU module 5.

FIG. 4 shows the internal bus timing of the operation sequence for reading the peripheral module 1 from the CPU module 5.

The CPU module 5 outputs the address to the address bus 10 at the rise of φ0 and the read signal 12 at the next fall.

The peripheral module 1 recognizes the LOW of the read signal 12 at the rise of φ1 and outputs the data to the data bus 11 at the next rise, and simultaneously sets the acknowledge signal 18 to the LOW.

When the CPU module 5 samples the acknowledge signal 18 at the falling edge of φ0 and recognizes LOW, it takes in the data on the data bus 11 at the next rising edge, and at the same time sets the read signal to High to the peripheral module 1. Notify that the read operation is completed. further,
Address output is stopped at the next rise of φ0.

When the peripheral module 1 recognizes the read signal 12High at the fall of φ1, the next rise of φ1
At the same time as stopping the output of data, the acknowledge signal 18
Is High.

The CPU 5 recognizes the acknowledge signal 18High at the falling edge of φ0, and the read cycle is completed.

The write operation from the CPU 5 to the peripheral module 1 is also executed by the same exchange by the write signal 13.

In FIG. 5, one clock generator 6
The clock generated by the frequency dividing circuit 19, 20, 2
Frequency division by 1, 22, 23, multiple clocks φ0, φ
This is an example of obtaining 1, φ2, φ3, and φ4.

At this time, the clock generated by the clock generator 6 is the CPU 5 and the peripheral modules 1, 2 ,.
It is necessary to set the frequency to the least common multiple required by 3 and 4. This is frequency-divided to generate a plurality of clocks, and the CPU and peripheral modules selectively connect and use the required clocks. The exchange between the CPU and the peripheral module is the same as in the case of FIGS.

In FIG. 6, clocks φ0, φ1, φ2, φ3, φ generated by frequency division from three clock generators 6, 28, 29 and the output of the clock generator 6 are generated.
Select from 4, φ5, φ6, peripheral modules 1, 2,
Supply to 3 and 4. The clock is selected by the selector 24,
25, 26, 27.

The clock selection controller 30 controls the selector. The setting value of the control unit 30 is written by the CPU module 5. In this example, the operating speed of the peripheral module can be arbitrarily selected.

[0035]

According to the present invention, the CPU module mounted on the single-chip microcomputer and the peripheral module operating with the clock have their own independent clock sources, operate with independent clocks, and
Since the exchange between the PU and each peripheral module is performed by handshake, layout design of clock wiring and the like is facilitated, the flexibility of the module is increased, and the performance of the entire microcomputer can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional example of a single-chip microcomputer.

FIG. 2 is an explanatory diagram showing a conventional example of internal bus timing.

FIG. 3 is a block diagram showing an internal configuration of a single-chip microcomputer according to an embodiment of the present invention.

FIG. 4 is a timing chart of an internal bus according to the embodiment of this invention.

FIG. 5 is a block diagram showing an internal configuration of a single-chip microcomputer according to an embodiment of the present invention.

FIG. 6 is a block diagram showing an internal configuration of a single-chip microcomputer according to an embodiment of the present invention.

[Explanation of symbols]

1, 2, 3, 4, ... Peripheral module, 5 ... CPU module, 6, 14, 15, 16, 17, ... Clock generator, 7 ... ROM, 8 ... RAM, 9 ... Port, 10 ... Address bus, 11 ... Data bus .

Claims (3)

[Claims] 1. In a single-chip microcomputer, among the modules mounted on the chip, the CPU and peripheral modules that operate on a clock operate on independent clocks, respectively, and the exchange between the CPU and each peripheral module is performed. , A single-chip microcomputer that operates by handshake. 2. The single-chip microcomputer according to claim 1, wherein each module has a clock generator, and thus a plurality of clock generators are provided on a chip. 3. The chip according to claim 1, comprising one or a plurality of clock generators in a chip, dividing a clock obtained from the clock generators to generate a plurality of clocks, and selecting a plurality of clocks from each of them. A single-chip microcomputer in which each module operates by selecting the clock required for.