KR100271714B1 - Column address internal counter - Google Patents

Abstract

PURPOSE: A column address internal counter device is provided to generate a carry at the same time when a counter block is set to reduce the time for generating the carry in order to accelerate the operation of the internal counter. CONSTITUTION: The column address internal counter device includes a counter block(10), a multiplexer(30) and a carry generator(20). The counter block includes a plurality of internal counter each of which stores external address simultaneously controlled by a set signal, an increment signal and the carry, and outputs internal addresses simultaneously. The multiplexer receives the external addresses and the internal addresses to output the external addresses or the internal addresses with response to the state of the set signal. The carry generator receives the external addresses or the internal addresses and outputs the carry to each internal counter of the counter block. The multiplexer further uses the set signal as an adjust signal to select the external address at the first address and to select the internal address of the counter block.

Description

Column Address Internal Counter Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for improving the speed of an internal counter in a semiconductor device, and more particularly to a column address internal counter device for speeding up a carry output of a carry generator.

1 shows a column address internal counter device according to the prior art, which comprises a plurality of internal counters for storing an external address, under control of a set signal and an increment signal, and outputting an internal address. The counter block 10 and the carry generator 20 which inputs and closes the said internal address and generate a carry with each internal counter of the said counter block are comprised.

The carry generator is responsible for accepting the current internal counter state and generating a carry telling which bits of the counter should be toggled on the next increment to be executed.

There are two main modes of operation: the first is an "set" operation that accepts an initial address and loads it into a counter block, and the second is an "increment" operation that translates to the next address. .

To perform an "increment", you must generate a carry that determines which bits to change in the current increment. This carry generation is performed in the above-mentioned carry generator.

In FIG. 1, the internal counter accepts the current state of the counter block as input data for the carry generation.

The timing of operation for the first clock cycle to accept an external address in this structure is shown in FIG.

The operation waits for an external address to come in and then emits a "set" signal.

The external address is stored in each internal counter of the counter block.

After the address signals of each internal counter are changed, they are output to the outside of the counter block, and the received signals are received and the carry generator makes a new carry and inputs to each internal counter.

The "increment" signal is generated as a rain after making the carry new.

Therefore, as described above, the minimum clock cycle time that can be provided by the counter device inside the column address becomes the time taken to go through all the above-mentioned processes. That is, the sum of the time it takes to set, the time it takes to generate a carry, and the time it takes to increment.

Thus, the occurrence of carry in time occurs after the counter block is set.

As described above, the "set" operation and the "increment" operation are connected in series, so that the operation speed of the internal counter becomes slow.

The present invention is to reduce the time it takes to generate a carry out of the clock time, thereby improving the operation speed of the internal counter.

Accordingly, the present invention was devised to solve the above-mentioned problem, and the operation speed of the internal counter is reduced by reducing the time for the carry generation by generating the carry at the same time as the counter block is set by receiving the external address directly as the input of the carry generator. It is an object of the present invention to provide an internal counter device for improving column address.

1 is a block diagram of a column address internal counter according to the prior art.

2 is an operation timing diagram with respect to FIG.

3 is a block diagram of a column address internal counter according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: counter block 20: carry generator

30: multiplexer

The column address internal counter apparatus of the present invention for achieving the above object is a counter block (10) comprising a plurality of internal counters controlled by a set, an increment signal and a carry to simultaneously store an external address and output an internal address simultaneously. ), A multiplexer 30 that accepts the external address and internal address and outputs the external address or internal address according to the state of the set signal, and accepts the external address or internal address and carries them to each internal counter of the counter block. It characterized in that it comprises a carry generator 20 for outputting.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a column address counter apparatus according to an embodiment of the present invention, which is controlled by a set, an increment signal, and a carry, and includes a counter block including a plurality of internal counters for simultaneously storing external addresses and simultaneously outputting internal addresses. 10, a multiplexer 30 that accepts the external address and internal address and outputs the external address or internal address according to the state of the set signal, and each internal counter of the counter block that accepts the external address or internal address. It consists of a carry generator 20 for outputting a carry.

The present invention differs from the prior art in that the input of the carry generator is controlled via a multiplexer.

Here, the set signal serves to store an external address in each internal counter in the counter block.

The increment signal is a signal in which each internal counter in the first counter block is operated by an external address, but then internally, an internal address is created and used.

The multiplexer takes the external address and the internal address and sends one of them to the output. It is determined by the state of the set signal.

The carry output from the carry generator is input to each internal counter of the counter block to determine whether data is toggled.

In operation, in the clock cycle that accepts an external address, the set signal input to the multiplexer is turned on to select an external address and send it to the carry generator. Otherwise, the set signal is turned off to select the current internal address of the counter block. Send it to the carry generator.

In the present invention, in the first clock cycle of accepting an external address, the carry generator may receive an external address and generate a carry before all the counter blocks are set. Therefore, the generation of the carry and the set operation of the counter block may be simultaneously performed.

Conventionally, the set operation and the increment operation are composed of a serial signal system, while in the present invention, the carry generation operation in the carry generator and the set operation of the counter block are simultaneously performed, so that at least one operation is required. Less time In other words, the maximum frequency at which the internal counter can operate can be increased.

The present invention can increase the processing speed of the counter, thereby increasing the maximum frequency that can be operated.

In addition, when operating at a frequency below the highest frequency, the timing margin between the counter setting and the adjustment signal for the increment can be increased to improve the yield, thereby lowering the price per chip, thereby increasing the price competitiveness.

Claims (2)

A counter block composed of a plurality of internal counters controlled by a set signal, an increment signal, and a carry to simultaneously store an external address and output an internal address, and accept the external address and the internal address and according to the state of the set signal And a multiplexer for outputting the external address or the internal address, and a carry generator for receiving the external address or the internal address and outputting a carry to each internal counter of the counter block. The column address of claim 1, wherein the multiplexer uses a set signal as an adjustment signal of the multiplexer to select an external address when the first address is accepted and to select an internal address of the counter block. Internal counter device.

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