JPH0478619U

JPH0478619U -

Info

Publication number: JPH0478619U
Application number: JP12169590U
Authority: JP
Priority date: 1990-11-19
Filing date: 1990-11-19
Publication date: 1992-07-09

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
である。第２図は第１図実施例の周波数・デユー
テイ変更回路の一例を示すブロツク図である。第
３図は第１図および第２図で示す実施例で得られ
るＣＰＵクロツクの例を示すタイミング図である
。第４図は第１図実施例の周波数・デユーテイ変
更回路の他の例を示すブロツク図である。図において、１０はＣＰＵ、１２はアドレスバ
ス、１４はデータバス、１８は第１メモリ、２０
は第２メモリ、２２はＩ／Ｏポート、２４，２８
，２８′はアドレスデコーダ、２６はＣＰＵクロ
ツク発生回路、３０は基準クロツク源、３２，３
２′は周波数・デユーテイ変更回路、４６はシフ
トレジスタを示す。 FIG. 1 is a block diagram showing one embodiment of this invention. FIG. 2 is a block diagram showing an example of the frequency/duty changing circuit of the embodiment shown in FIG. FIG. 3 is a timing diagram showing an example of the CPU clock obtained in the embodiment shown in FIGS. 1 and 2. FIG. 4 is a block diagram showing another example of the frequency/duty changing circuit of the embodiment shown in FIG. In the figure, 10 is a CPU, 12 is an address bus, 14 is a data bus, 18 is a first memory, and 20
is the second memory, 22 is the I/O port, 24, 28
, 28' is an address decoder, 26 is a CPU clock generation circuit, 30 is a reference clock source, 32, 3
2' is a frequency/duty changing circuit, and 46 is a shift register.

Claims

[Claims for Utility Model Registration] 1. A clock switching circuit for providing a CPU clock to a CPU, comprising: address decoder means for decoding the address of the CPU and outputting a plurality of decoded signals; and a reference clock for generating a reference clock. and a clock generating means for processing the reference clock to generate the CPU clock at different frequencies depending on the plurality of decoded signals from the address decoder means. 2. The clock switching circuit according to claim 1, wherein said clock generating means generates said CPU clock with a different duty ratio according to said plurality of decoded signals.