JPS6020243A - Central arithmetic processing circuit application device - Google Patents

Abstract

PURPOSE:To select the operation speed of the program suitable for the user, by providing the function which can vary the operation speed of the program. CONSTITUTION:CPU1 reads the memory contents of the system ROM2 through the data bus 4. The clock signal needed for CPU1 to operate is generated by the clock occurrence circuit 7. The operation speed variable circuit 16 is installed between the CPU1 and clock occurrence circuit 7. The operation speed of CPU1 is varied freely by thinning the clock signal in accordance with the needs. This operation speed variable circuit 16 consists of the address identification circuit 12, operation speed setting circuit 13, delay signal occurrence circuit 14 and operation temporary stop circuit 15.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a device, such as a burner computer, that uses a central processing circuit that is integrated on a large scale, and particularly relates to a device that uses a central processing circuit that is integrated on a large scale, and in particular to a device that allows the operating speed of a program to be varied. The present invention relates to a variable operating speed function suitable for

[Background of the invention]

Conventionally, in devices using a central processing circuit (hereinafter abbreviated as CPU), many devices use a clock signal with a predetermined fixed frequency as the clock signal for the CPU (the operating speed of the CPH There was almost no way to make the operating speed variable within the range of conventional technology: (1) change the original oscillation circuit to a variable frequency oscillation circuit; (2) use multiple systems with different frequencies. There were methods such as setting up and switching oscillation circuits and using them.However, in game devices and personal computers that use a CPU, peripheral elements and devices often require a clock signal of a constant frequency. Furthermore, in order to drive these peripheral elements and devices with good movement, it was necessary to match the operation clock signals of the 02 ports with these clock signals.Therefore, in game devices and personal computers, the CPU Most of the programs use a fixed frequency signal as the potter's wheel chime signal, and there are only those that can switch between two types of clock signals using the method (2) mentioned above, which allows you to freely control the operating speed of the program. The drawback was that it could not be changed.

For example, since the operating speed for a certain program is constant, even if the operating speed is optimal for a person skilled in the program, the operating speed may be too fast for a beginner. Moreover, even if the operating speed is optimal for a beginner, the operating speed may be too slow for an experienced user, resulting in a problem in operability.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to
To provide CPU application devices such as game devices and personal computers that have a function that allows the user to vary the operating speed of the program that is most suitable for the user, even if the device uses a fixed frequency signal as the PU clock signal. be.

[Summary of the invention]

In order to achieve the above object, the present invention includes an address identifying means for identifying an address range in which a predetermined program is executed, an operating speed setting means for setting an operating speed of the grogram, and an address identifying means for setting the operating speed of the program. delay signal generating means for generating a delay signal corresponding to the set value set by the operation speed setting means based on the identification signal outputted from the CPU; An operation temporary stop means for stopping the operation is provided.Thereby, the address identification means identifies that the CPU is operating in a certain address range, and the setting value set by the operation speed setting means based on the identification signal is provided. The delay signal generating means generates a delay signal corresponding to CP[J.
The operation of the apparatus is temporarily stopped, and the operation speed can be varied by the operation speed setting means.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the CP (J application device) according to the present invention. In the figure, 1 indicates CPIJ,
2 is a system memory (hereinafter referred to as system ROM) for storing the operating program of the CPU, 3 is a memory for storing data (hereinafter referred to as data RAM), and 4 is the 02 port for storing peripheral circuits and data. 5h CPU address bus for sending and receiving data, 6
7 is a control bus, 7 is a klovk generation circuit, 8 is an expansion memo 1c that is used to expand the system's functions, 9 is C
A display interface circuit serves as an output circuit for the PU; 10 is a keyboard; and 11 is a keyboard interface circuit that serves as an input circuit for the CPU. Further, 16 is an operation speed variable circuit, which is composed of 12 address identification circuits, 13 operation speed setting circuits, 14 delay signal generation circuits, and 15 operation temporary stop circuits.

Further, FIG. 2 is a diagram showing an example of address assignment of the CPU application device shown in FIG. 1. In FIG. 1, a CPU 1 is a central processing circuit called a microcomputer. Usually, the CPU 1 can perform multiple and soto arithmetic processing at the same time, but in this example, for convenience of explanation, it is assumed to be a CPU capable of 8-pi soto parallel processing, and the address bus 5 has 16 differential lines output, and the n1 control bus 6 has Assume that there is only a read/write control signal. CPU1 is from address 0 to 655
Address 65 (If expressed in hexadecimal, it becomes address FFFF, which is easier to express, so the following addresses will be expressed in hexadecimal)
As shown in FIG. 2, each circuit is separated by address. That is, the system ROM 2 stores the system processing procedures (programs).
has a total capacity of 8 kilobytes from (Eooo) 16 address to (FFiF) address 16, data R^M3 has a total capacity of 4 kilobytes from address 0 to (0FFF) 16, and in the display interface circuit 9. The built-in display memory has a total capacity of 16 kilobytes allocated from address 16 to (BFFF) + 6 on (80aO).The remaining addresses are reserved for expansion memo!78[1!I]. In addition, there are input/output control addresses used for the keyboard interface circuit 11 and display interfaces other than the display memory, but they only require a few bytes in terms of capacity, so they are not shown in Figure 2. It is omitted.

Now, the general operation of the Brolik diagram shown in FIG. 1 will be explained below. First, 02 port 1 is the command f;r of system ROM2.
: To read, a specific address of the system ROM 2 is output to the address bus 5, a read signal is output to the control bus 6, and the stored contents of the system ROM 2 are read via the data bus 4. The system executes these commands one after another as commands, changes the stored contents of the data RAM 3 and display memory, reads press information on the keyboard 10 via the keyboard interface circuit 11, and receives and receives data from the input/output circuit. make it work. At this time, the clock generating circuit 7 is a circuit that generates a fixed frequency clock signal necessary for the operation of the CPU 1. Required for CPU1
There are two types of signals depending on the type of C'PU.

One is 1 Hitachi, Ltd. CPU%HD46800
There is one type in which one bus cycle corresponds to one black cycle, and the other type is a CPU made by the same company, HD680.
9, NEC Corporation's CPU, μP0780, etc., where one bus cycle is a plurality of cycles. Regardless of which clock signal is used, the operating speed of the CPU 1 can be arbitrarily varied by providing an operating speed variable circuit 16 between the clock generating circuit 7 and the CPU 1 and thinning out the clock signals as necessary. .

For example, the address identification circuit 12 may cause the expansion memory 8 to
When the system program identifies the address range assigned to n, generates a delay signal in the delay signal generation circuit 14, and supplies it to the operation pause circuit 15, the system program operates at a certain operation speed, but the delay signal is not stored in the extended memory 8. When executing a program, the operating speed can be varied by the operating speed setting circuit 13. The operating speed is
It is stored in the extended memory 8 and can be changed even while the program is being executed.

FIG. 3 is a circuit diagram showing a specific example of the variable operating speed circuit 16 in FIG. 1, and FIG. 4 is a signal waveform diagram of each part for explaining FIG. In FIG. 3, 17 is an NAND circuit corresponding to the address identification circuit 12, and 18 is a monostable multivibrator circuit corresponding to the delay signal generation circuit 14. The monostable multivibrator circuit 18 includes a capacitor C that determines the output pulse width and a variable resistor V.
Ft is connected, and the variable resistor VR corresponds to the operating speed setting circuit 13 in FIG. Further, 19 is a bistable multivibrator circuit with a clear input terminal (hereinafter abbreviated as DFF circuit), 20 is an OFF circuit, 21 is a NOT circuit, 2
2 is an AND circuit. Further, signal paths 30 to 35 are shown in FIG. 4, and examples of signal waveforms of signal paths 9 and n are shown in FIG.

In FIG. 5, the clock generation circuit 7 is shown in FIG.
Periodicity as shown in . It generates a black signal of NO
It is supplied to the DFF circuit 200GK input terminal and one input terminal of the AND circuit 22 via the 'f' circuit 21. N
The input terminal of the AND circuit 17 is supplied with the address bus 5 and the control bus 6, and if the condition of this input terminal does not meet the predetermined address condition, the output of the NAND circuit 17 remains at a high level. It is.

Then, via signal path 30.3L33.34, AND
The other input of the circuit 22 becomes −・Irepel, and AN
A clock signal supplied from the clock generation circuit 6 appears at the output terminal of the D circuit 22. This clock signal is supplied to the CPU1 via the signal path 35 and
The CPU of the D46800 will execute the instruction at the next address. However, if the address of the executed instruction meets a predetermined address condition,
The output of the NAND circuit 17 generates an identification signal as shown in FIG. 4 (CG). In response to this identification signal, the monostable multivibrator circuit 18 generates a delay signal with a pulse width T determined by the MJK resistor VR and the capacitor C as shown in FIG.
The signal is output to the signal path 31 as shown in FIG. DFF' circuit 19
As shown in FIG.
It is reset when it is transmitted via signal path 33. Therefore, the output signal of the OFF circuit 20 is as shown in FIG.
As shown in K, as clock signal No. 11, which holds the low level for a 'ro period from the second falling edge of the clock signal that comes after the rising edge 9 timing of the delayed signal, AN
It is supplied to the D circuit η. When the clock gate signal is at a low level, the clock signal is not output from the gate, and is supplied to the CPU 1 as a signal as shown in the fourth diagram. As a result, when the predetermined identification address conditions are satisfied, the operating speed of the CPU 1 is reduced by the gate time of the clock signal.

Next, the relationship between the pulse width T of the delay signal and the operating speed will be further explained. FIG. 5 is a diagram explaining these relationships. When all the addresses output from the CPU meet the predetermined identification address conditions, the CPU 1 This figure shows how the clock signal supplied to the system changes. In the same figure, s lal + (bl I lal indicates the case where the identification address condition is satisfied as in Fig. 4. In addition, the delay signal has a pulse width "(0<T
, < Ti), the clock gate signal becomes (e
It becomes a low level every cycle of the clock signal as shown in (f), and is supplied to the CPU 1 as shown in (f).
The Rurijirozuku signal is half the peak of (al). Therefore, the operating speed is also reduced to half. In other words, when the delay signal has a pulse width T2 (9≦'I'2<yTo), wave 1, t
hl, (as shown in il, the clock signal supplied to CPU1 is 168 oh, 1, 1 yu, 7.10>
7 @ T 5゜ ('T'o≦T s <T'o)
') Time h, (jl, (kl, (1+ vc
The clock signal supplied to KCPUl is multiplied by 1.

In this way, the clock signal supplied to the CPU 1 can be freely varied by a factor of 1 depending on the pulse width of the delay signal. (N is a natural number greater than 2)
Therefore, in the circuit example of FIG. 3, the operating speed can be varied up to T times.

FIG. 6 is a circuit diagram showing another specific example of the variable operating speed circuit 16 in FIG. 1, and the same circuits as in FIG. 3 are given the same reference numerals. The major difference from FIG. 3 is that the DFF circuit 19 is omitted and the delayed signal, which is the output of the monostable multivibrator circuit 18, is directly input to the DFF circuit 20 via the signal path 31. . With such a circuit configuration, the clock gate signal outputted to the signal path 34 can be kept at a low level for several clock cycles, so that the operating speed can be reduced to less than one time.

FIG. 7 shows another embodiment according to the present invention, which is basically the same as the embodiment shown in FIG. 1, but is an example of a circuit where the CPU is provided with an input for suspending operation. In the same figure, 23 is a decoder circuit corresponding to the address identification circuit 12 in FIG. 1, 24 is a shift register circuit, and 25 is a NO.
The T circuit and 26 are OR circuits. In addition, the shift register circuit 24NOT circuit 25. In the OR circuit 26, a switch SW, which corresponds to the delay signal generation circuit 14 and selects each output of the shift register circuit 24 and supplies it to the CPU 1 as a delay signal, is connected to the first factor operating speed setting circuit 13. .

The circuit consists of a signal line connected to the clock signal input terminal of CPIJl and a ready input or wait input terminal, and a part of the CPU 1, which corresponds to the first cause operation temporary stop circuit 15. Ruru. FIG. 8 is a diagram of signal waveforms of various parts for explaining the operation of the circuit of FIG. 7. The clock signal shown in FIG. 8 1a) Ic is the HD
This is a waveform diagram when used in a 6809 type CPU, and shows the case where four clocks correspond to one bus cycle as shown in (b). When the a and b terminals of the switch sw are connected, a predetermined identification address is output to the address bus 5 as shown in Figure 8 (bl).
1 decoded by the encoder 3o and sent to the signal path 30 (c
Even if an identification signal such as l is output n, the delayed signal on the signal path 31 will never go to low level. The NOT circuit 25 and the OR circuit 26 are used to apply a clear signal to the clear terminal CR of the shift register circuit 24 when the identification signal reaches the lowest point at 9 o'clock. Qm to Ql of the shift register circuit 24
Until one'tn-t:n output is cleared after n.

The circuit maintains a low level for the number of corresponding clock signals. Therefore, the C terminal of switch SW and C
When the terminals are connected, FIG. 8(e).

(As shown in fl, t81, the bus cycle will be extended by 7. Furthermore, when the C terminal and the d terminal are connected, FIG. 81)) l, tel,
(jl ÷ bus cycle will be lengthened. Furthermore, the operation speed of this circuit configuration is the slowest when the C terminal and 8 terminal of the Suibuchi SW are connected, as shown in Fig. 8 (k
).

(nl, (m+) is ÷ bus cycle length. Therefore, in the circuit example of FIG. 7, the Tekota 3
Programs in the address range that can be identified by 0 from 1 to 1
This means that the operating speed can be freely varied within the range of up to double the operating speed.

Of course, specifying the address range is not limited to the memory where the tourogram is stored; for example, you can also set the address range to the display memory as shown in Figure 2, and the operating speed of the program related to the thorny display can be similarly varied. Become.

In addition, depending on the system configuration, a dynamic RAM is used as the data storage memory, and the CPU performs seven revisions, so the CPU
Although there are cases where it is not possible to stop the U bus cycle, the present invention can be implemented by detecting the occurrence of a delay signal of a certain pulse width or more and using a separate dynamic I-type RAM board.

9 and 10 show examples of embodiments of the present invention. In the 9th edition, an operating speed setting knob was installed on the main body of the personal computer, and the address identification range was assigned to the extended memory. An example in which this is possible is shown in Fig. 10, in which an operating speed setting knob is provided on the ROM cartridge side to be inserted. C signal extended memory 8
Even if the signal is supplied in common to the delay signal generating circuit 14 and the delay signal generating circuit 14, the function of freely changing the operating speed remains unchanged, and the operating speed can be changed with a simpler circuit configuration.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a CPC application device that uses a fixed frequency signal as a clock signal with a new function that allows the user to set an operating speed of 10 g that is optimal for him/her. can. Also, due to this,
The program is full of content! Operability is improved because the operating speed can be set according to the speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the CP port application device according to the present invention, FIG. 2 is a diagram showing a part of the address assignment of the device in FIG. 1, and FIG. 3 is the operation in FIG. 1. 4 and 5 are signal waveform diagrams for explaining Figure 3, and Figure 6 is a diagram showing a specific circuit example of the variable speed circuit.
7 is a diagram showing another embodiment of the present invention, FIG. 8 is a signal waveform diagram for explaining FIG. 7, and FIG. , FIG. 10 is a diagram showing an embodiment of the present invention. 1...CPU, 2...System ROM% 3...
Data RAM, 8... Expansion memory, 7... Clock generation circuit, 12... Address identification circuit, 13...
Operating speed setting circuit, 14... Delay signal generation circuit, 15
. . . Operation temporary stop circuit, 16 . . . Operation speed variable circuit. Figure 3, figure 4, figure 5 ()) Pl, /clock master, Figure 8, IO, day ROM curl, person who makes corrections once, patent applicant?・ Name +510) Hayashi Shikikai 11 Made by Hitachi f ¥
Figures 9 and 10 of the appendix show examples of embodiments of the present invention. In FIG. 9, an operating speed setting knob 67 is provided on the main body of the personal computer 36, the address identification range is set to the address assigned to the extended memory, and the operating speed is changed when the ROM cartridge 38 is inserted and the program in the cartridge is executed. Here is an example that made it possible. 1st
Figure 0 shows an example in which an operating speed setting knob 40 is provided on the side of the ROM card (IJ) 39 to be inserted. In this case, as shown in the figure, even if a signal already decoded for the expansion memory 8 is commonly supplied to the expansion memory 8 and the delay signal generation circuit 14, the function of freely changing the operating speed remains unchanged. Operation speed can be varied with a simple circuit configuration. Note that 41 in the figure is an expansion bus connection terminal.

Claims (1)

[Claims] The central processing circuit layer (hereinafter referred to as C
In a CPU application device equipped with a CPU (abbreviated as PU), an address identifying means inputs an address signal output from the CPU and identifies a predetermined address range, and an operation for setting the operating speed of the CPH. a speed setting means; a delay signal generating means for receiving the identification signal output from the address identification means and generating a delay signal corresponding to the set value set by the operation speed setting means; An operation suspension means is provided for inputting the output pulse signal of the oscillation circuit and temporarily suspending the processing operation of the CPU by reducing the number of pulses of the pulse signal using the delay signal, and the CPU is provided with an operation suspension means for temporarily suspending the processing operation of the CPU. 1. A CPO application device, characterized in that the operating speed can be varied by the operating speed setting means during operation.