JPS62159265A - Data transfer system - Google Patents

Abstract

PURPOSE:To transfer the picture data to a memory at a high speed by having different arrangements of memories between a data transfer mode and a MPU processing mode. CONSTITUTION:In a data transfer mode the chip selection signal is outputted to a signal line 19 from an address generator 8 so that memories 2-5 are all validated. Thus the data on a data bus 12 can be transferred all at once to the designated addresses of memories 2-5. In an MPU processing mode the lower 2 bits of the address produced by an MPU1 are decoded by an address decoder 9. Then the memories 2-5 are successively validated for each increment of the address. Thus the chip selection signal can be outputted onto a signal line 18.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a microprocessor (hereinafter referred to as MPU).
The present invention relates to a data transfer method that transfers data at high speed using .

(Prior Art) When attempting to transfer data having a data width greater than the data length (word length) that can be processed at one time by an MPU to a memory at high speed, an effective data transfer circuit is required. MPU
Data processing using this method is used in various fields, and there is an increasing demand for high-speed processing of heavy snow data.

An example of a data processing circuit according to the prior art is shown in FIG.

In Fig. 6, l is MPU, and 2 to 5 are memory l.
J, 21 is a multiplexer, 91 is an address decoder,
11 is a data bus, and 141 is an address bus.

As shown in FIG. 6, in a data processing circuit using an MPU, the width of the data bus 11 is limited by the word length (N bits) of the MPUI because data processing is executed by the MPU. Therefore, as shown in FIG. 7, the memories 2 to 5 are arranged so that four word length data are arranged in units of one word length. Therefore, the data width of 4 words long on the data bus 121 is converted to 1 word length by the multiplexer 21, and the data transfer to the memories 2 to 5 via the data bus 11 is also 1 word long.
It was necessary to do it in units of candy chiefs.

(Problems to be Solved by the Invention) In the conventional data transfer circuit described above, data transfer to the memory is limited to one candy length unit. For this reason,
Data on the data bus 121 with a data width greater than the above is converted into data with a width of one piece by the multiplexer 21, and then it is necessary to transfer it to the memories 2 to 5 in several parts, which increases the speed of data transfer. It had the disadvantage of being limited.

For example, in the case of position detection of a two-dimensional image, it is necessary to process three types of image data: horizontal address, vertical address, and No. 48 level, and all data is transferred in units of 1 candy length as in the past. However, due to time constraints, it was not suitable for data that required high speed, such as moving image data, which was a problem.

An object of the present invention is to change the memory arrangement during data transfer and MP
By switching between U and U processing and selecting data to achieve high speed and appropriate memory layout, the disadvantages of SI are removed, and even data with a data width exceeding the predetermined length of the MPU can be processed at high speed. An object of the present invention is to provide a data transfer method configured to enable data transfer.

(Means for Solving the Problems) The data transfer method according to the present invention includes a microprocessor,
It is configured to include a plurality of memories, a plurality of selection means, an address generator, and an address decoder.

Microprocessors are for processing data.

The plurality of memories are for storing data processed by the microprocessor.

The multiple selection means are for transferring data to multiple memories at high speed, and are for switching the data at high speed and memory arrangement between data transfer and MPU processing, and each corresponds to multiple memories. It is.

The address generator is for providing addresses to multiple memories.

The address decoder is used to change the address so that the data transferred to the memory during data transfer can be effectively processed during MPU processing.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment for realizing a data transfer method according to the present invention. In Figure 1,
1 is an MPU, 2 to 5 are memories, 7 is an address bus selector, 8 is an address generator, 9 is an address decoder, 61 to 64 are data bus selectors, 201
~204 are chip select signal selectors, lo
12 are data buses, 13 to 15 are address buses, 16 are select signal lines, and 17 to 19 tri are chip select signal lines.

In FIG. 1, the select signal on the signal line 16 controls the data bus selectors 61 to 64, the address bus selector and the chip select signal selectors 201 to 204, and controls the memory 2 to 20 during data transfer and MPU processing. Data buses 10-12.5 are connected to data buses 10-12. Address bus 13-15
, and chip select signal lines 17 to 19 are selected as follows.

First, during data transfer, the data bus 12, address bus 15, and chip select signal M19 are selected by the select signal on the signal line 16 and connected to the memories 2-S.

Second, during MPU processing, the select signal on the signal 516 is used to select the υ data path 11. Address bus 14 and chip select signal [18] are selected and connected to memories 2-5.

As a result of the above switching, the circuit #5 configuration and memory arrangement at the time of data transfer become as shown in FIG. 2 and FIG. 8, respectively. Further, the circuit configuration and memory arrangement during MPU processing are shown in FIGS. 4 and 5, respectively.

Hereinafter, the operation of the circuit and the state of data will be explained with reference to FIGS. 2 to 6.

In FIG. 2, the address generator 8 outputs the chip selenoid 2= signal to the signals i17-19 so that all of the memories 2-5 are valid during data transfer. As a result, the data bus 12 (4
(assuming data of word length and width) can be transferred at once to addresses in memories 2 to 5 designated by address generator 8.

During MPU processing, as shown in Figure 4, the lower two bits of the address generated by the MPU are decoded by the address decoder S, and the chip is decoded so that memories 2 to 5 are sequentially enabled each time the address is incremented. A select signal is output on signals #17 to #19. This results in
The memory arrangement shown in FIG. 8 is converted as shown in FIG. 5, and a memory arrangement similar to the conventional one is obtained. By the above operation, the MPU processing can be executed in the same manner as before.

(Effects of the Invention) As described above, the present invention has the effect that loud data can be transferred to the memory at high speed by switching the memory arrangement between data transfer and MPU processing.

If the present invention is used, for example, to detect the position of a two-dimensional image that requires high speed, it becomes possible to transfer image data to memory at high speed.On the other hand, since the MPU is not required during data transfer, It can also be used for program processing, and has the effect of greatly increasing processing speed and efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment for realizing a data transfer method according to the present invention. FIG. 2 is a block diagram showing the configuration of the data transfer method shown in FIG. 1 during data transfer. FIG. 8 is an explanatory diagram showing a memory arrangement during data transfer using the data transfer method shown in FIG. 1. FIG. 4 is a block diagram showing the configuration of the data transfer method shown in FIG. 1 during MPU processing. FIG. 5 is an explanatory diagram showing the memory arrangement during MPU processing of the data transfer method shown in FIG. 1. FIG. 6 is a block diagram showing an example of a data processing circuit employing an MPU according to the prior art. FIG. 7 is an explanatory diagram showing the memory arrangement of the data processing circuit shown in FIG. 6. l@Bone/MPU 2-5...Memory 61-64...Data bus selector 7...Address bus selector 8...Address generator 9.91--Address decoder 201-204...-Chip Select signal selector 21...Multiplexer 10~12.121---Data bus 13~15.141'...Address bus 16...Select signal line 17~19.181---Tep select signal Fig. 2 Figure 3

Claims (1)

[Claims] a microprocessor (MPU) for processing data; a plurality of memories for storing data processed by the microprocessor; and a device for transferring the data to the plurality of memories at high speed. Said MPU
a plurality of selection means corresponding to the plurality of memories for switching the data bus width and memory arrangement during processing; an address generator for giving addresses to the plurality of memories; A data transfer system comprising: an address decoder for changing addresses so that the transferred data can be effectively processed during the MPU processing.