JPS62159007U - - Google Patents
Info
- Publication number
- JPS62159007U JPS62159007U JP4768186U JP4768186U JPS62159007U JP S62159007 U JPS62159007 U JP S62159007U JP 4768186 U JP4768186 U JP 4768186U JP 4768186 U JP4768186 U JP 4768186U JP S62159007 U JPS62159007 U JP S62159007U
- Authority
- JP
- Japan
- Prior art keywords
- charging
- mute
- during
- transistor
- period
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007599 discharging Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Television Receiver Circuits (AREA)
- Control Of Amplification And Gain Control (AREA)
- Noise Elimination (AREA)
Description
第１，２図は、それぞれこの考案のミユーテイ
ング回路の一実施例を示す回路図及び回路各部の
信号波形図、第３，４図は、それぞれ従来のミユ
ーテイング回路の一例を示す回路図及び回路各部
の信号波形図である。
１１…ミユーテイング回路、１１ａ…ミユート
入力端子、１１ｂ…ミユート出力端子、１２…充
・放電回路、Ｑ１…入力トランジスタ、Ｑ０…出
力トランジスタ。
Figures 1 and 2 are a circuit diagram and signal waveform diagrams of various parts of the circuit, respectively, showing an embodiment of the muting circuit of this invention, and Figures 3 and 4 are circuit diagrams and signal waveform diagrams of various parts of the circuit, respectively, showing an example of a conventional muting circuit. FIG. DESCRIPTION OF SYMBOLS 11... Muteing circuit, 11a... Mute input terminal, 11b... Mute output terminal, 12... Charging/discharging circuit, Q1 ... Input transistor, Q0 ... Output transistor.
Claims (1)
により導通する入力トランジスタと、この入力ト
ランジスタの導通期間に放電し、非導通期間中は
充電される充・放電回路と、この充・放電回路の
充電期間中導通する出力トランジスタと、この出
力トランジスタと前記入力トランジスタの導通期
間中接地されるミユート出力端子とからなるミユ
ーテイング回路。 An input transistor that is made conductive by a mute pulse applied to the mute input terminal, a charging/discharging circuit that is discharged during the conductive period of this input transistor and charged during the non-conducting period, and a charging/discharging circuit that is conductive during the charging period of this charging/discharging circuit. A muting circuit comprising an output transistor and a mute output terminal that is grounded during conduction of the output transistor and the input transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4768186U JPS62159007U (en) | 1986-03-31 | 1986-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4768186U JPS62159007U (en) | 1986-03-31 | 1986-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62159007U true JPS62159007U (en) | 1987-10-08 |
Family
ID=30868514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4768186U Pending JPS62159007U (en) | 1986-03-31 | 1986-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62159007U (en) |
-
1986
- 1986-03-31 JP JP4768186U patent/JPS62159007U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS62159007U (en) | ||
| JPS6293831U (en) | ||
| JPS60169989U (en) | data acquisition circuit | |
| JPS6356826U (en) | ||
| JPS6123740U (en) | Digital/analog conversion circuit | |
| JPS6172933U (en) | ||
| JPS62133496U (en) | ||
| JPS6183338U (en) | ||
| JPS62203519U (en) | ||
| JPS6150335U (en) | ||
| JPS63131417U (en) | ||
| JPS637823U (en) | ||
| JPS6037874U (en) | Pulse width to voltage converter | |
| JPS621430U (en) | ||
| JPS63111013U (en) | ||
| JPS6451324U (en) | ||
| JPS6242334U (en) | ||
| JPS5837212U (en) | Muting circuit | |
| JPS6188335U (en) | ||
| JPS6251825U (en) | ||
| JPS63185319U (en) | ||
| JPS6335145U (en) | ||
| JPS63108218U (en) | ||
| JPS6142660U (en) | double integrator circuit | |
| JPS6399424U (en) |