JPS62156900A - Manufacture of thick film circuit board - Google Patents

Manufacture of thick film circuit board

Info

Publication number
JPS62156900A
JPS62156900A JP29743185A JP29743185A JPS62156900A JP S62156900 A JPS62156900 A JP S62156900A JP 29743185 A JP29743185 A JP 29743185A JP 29743185 A JP29743185 A JP 29743185A JP S62156900 A JPS62156900 A JP S62156900A
Authority
JP
Japan
Prior art keywords
thick film
film circuit
alignment mark
alignment
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29743185A
Other languages
Japanese (ja)
Inventor
雅雄 瀬川
克也 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP29743185A priority Critical patent/JPS62156900A/en
Publication of JPS62156900A publication Critical patent/JPS62156900A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明はスクリーン印刷法による厚膜回路基板の製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a thick film circuit board using a screen printing method.

[発明の技術的背景とその問題点] 一般に厚膜回路を製造するには次のような方法により行
なわれている。まず第4図(a)に示すようにアルミナ
等の絶縁基板1上にあらかじめ所定の回路サイズを得る
ために、レーザー光線により基板外形溝2を形成し、こ
の基板外形溝2内に例えば銀パラジウムを含む導体ペー
ストを第4図(b)に示すようにスクリーン印刷し、焼
成して第1導体層3を形成する。この印刷の際には次工
程で印刷する配線層の位置合わせの基準となる位置合わ
せマーク4を複数個同時に印刷しておく。
[Technical background of the invention and its problems] Thick film circuits are generally manufactured by the following method. First, in order to obtain a predetermined circuit size on an insulating substrate 1 made of alumina or the like, as shown in FIG. The conductive paste contained therein is screen printed as shown in FIG. 4(b) and fired to form the first conductive layer 3. During this printing, a plurality of alignment marks 4 are printed at the same time to serve as a reference for alignment of the wiring layer to be printed in the next step.

そしてそのうち、この位置合わせマーク4に円中心が一
致するように例えば第4図(C)に示すように酸化ルテ
ニウム系抵抗体ペーストにより抵抗体層5とともに位置
合わせマーク6をスクリーン印刷等により印刷し、焼成
して形成する。このようにして順次任意の層数印刷して
厚膜回路を形成する。この方法では第1配線層が第1導
体層であれば第4図(b)に示すように最も基板外形溝
に近い配線層と外形間のクリアランスa、 a’を一定
に管理することで現物合わせて回路を印刷することがで
きた。
Then, in order to align the center of the circle with the alignment mark 4, for example, as shown in FIG. 4(C), an alignment mark 6 is printed together with the resistor layer 5 using ruthenium oxide resistor paste by screen printing or the like. , formed by firing. In this way, a thick film circuit is formed by sequentially printing an arbitrary number of layers. In this method, if the first wiring layer is the first conductor layer, the actual I was able to print the circuit accordingly.

しかしながら第5図(b)に示すように第1配線層が例
えば抵抗体層5の場合は位置合わせの管理が非常に困難
であった。
However, as shown in FIG. 5(b), when the first wiring layer is, for example, a resistor layer 5, it is very difficult to manage the alignment.

すなわら第5図(b)に示すように基板外側から位置合
わせマーク6までの距離す、 b’を管理して位置合わ
せを行なうことができるが、アルミナ基板のように基板
外形にばらつきか±1%もあるのでは第1配線層で形成
済の位置合わせマークを信用して位置合わせを行なうと
第5図(C)に示すように基板外形溝2より第2配線層
である第1導体層3がはみ出してしまうことがあった。
In other words, as shown in Fig. 5(b), alignment can be performed by controlling the distance (b') from the outside of the board to the alignment mark 6; however, unlike an alumina board, there may be variations in the board outline. Since the difference is as much as ±1%, if alignment is performed by trusting the alignment marks already formed in the first wiring layer, the first wiring layer in the second wiring layer will be aligned from the substrate outer groove 2 as shown in FIG. 5(C). The conductor layer 3 sometimes protruded.

これはレーザー光線による基板外形溝加工が基板外形を
治具につき当てて行なうことも原因となっている。この
ように位置合わせが困難ななめ品質低下や歩留り低下を
きたすという問題が生じていた。
This is also due to the fact that when machining grooves on the substrate outer shape using a laser beam, the outer shape of the substrate is brought into contact with a jig. As described above, there has been a problem in that alignment is difficult, resulting in deterioration in quality and yield.

[発明の目的] 本発明はこのような問題を解決するためなされたもので
、信頼性の高い厚膜回路を簡便に製造する方法を提供す
ることを目的とする。
[Object of the Invention] The present invention was made to solve such problems, and an object of the present invention is to provide a method for simply manufacturing a highly reliable thick film circuit.

[発明の概要] すなわち本発明は、レーザー光線により基板外形溝の形
成された絶縁基板上に厚膜回路を形成するに必たり、前
記絶縁基板の回路形成不要部に位置合わせマークを前記
基板外形溝の形成時にレーザー光線により形成し、この
位置合わせマークを基準にして各層を形成することを特
徴としている。
[Summary of the Invention] That is, in the present invention, when a thick film circuit is formed on an insulating substrate in which a substrate outer groove is formed using a laser beam, an alignment mark is placed in a portion of the insulating substrate where circuit formation is not necessary, in the same manner as in the substrate outer groove. It is characterized in that it is formed using a laser beam when forming the alignment mark, and each layer is formed using this alignment mark as a reference.

[発明の実施例] 次に本発明の一実施例について図面を用いて説明する。[Embodiments of the invention] Next, one embodiment of the present invention will be described using the drawings.

なお第4図および第5図と共通する部分は同一符号で示
した。
Note that parts common to FIGS. 4 and 5 are indicated by the same reference numerals.

まず第1図(a)に示すようにパワー出力5w、モード
系7龍φのYAGレーザー光線を用いて絶縁基板1上に
基板外形溝2と位置合わせマーク7をパルスモードで数
回、所定個所に照射することにより成形した。位置合わ
せマーク7は0.2+nmφ程度のランドを形成した。
First, as shown in FIG. 1(a), using a YAG laser beam with a power output of 5W and a mode system of 7 φ, the substrate outer groove 2 and the alignment mark 7 are formed on the insulating substrate 1 in a pulse mode several times at predetermined locations. It was shaped by irradiation. The alignment mark 7 formed a land of approximately 0.2+nmφ.

次にこの位置合わせマーク7に円中心が一致するように
、酸化ルテニウム粉末を含む抵抗体ペーストにより抵抗
体印刷用位置合わせマーク6を、第1配線層である抵抗
体層5とともに印刷及び補正し、150℃、10分間の
乾燥および850°C110分間の焼成により形成した
Next, a resistor printing alignment mark 6 is printed and corrected together with the resistor layer 5, which is the first wiring layer, using a resistor paste containing ruthenium oxide powder so that the center of the circle matches this alignment mark 7. , dried at 150°C for 10 minutes, and fired at 850°C for 110 minutes.

そのうち第1図(C)に示すように第2配線層である第
1導体層3を印刷するわけであるが、この時も形成済位
置合わせマーク7と導体印刷用位置合わせマークレーザ
ー光線とが円中心が一致するように補正を加えながら銀
パラジウム系導体ペーストを精度よく印刷し、乾燥、焼
成して第1導体層3を所定の基板外形溝2内に精度よく
形成できた。 なおレーザー光線による位置合わせマー
クは上記実施例のほかに例えば第2図に示すように抵抗
体印刷用位置あわせマーク6や導体印刷用位置合わせマ
ーク4の大きさく例えば0.4mmφ)よりやや大きめ
の、例えば0,5龍φの丸穴7aとしたり、あるいは第
3図に示すようにX、Yの直線すなわら十字状7bとし
、その交点に抵抗体印刷用位置合わせマーク6や導体印
刷用位置合わせマーク4がくるようにすることもできる
。その他四角、三角等の角形状やかぎ状などいろいろな
形状とすることができる。
As shown in FIG. 1(C), the first conductor layer 3, which is the second wiring layer, is printed. At this time, the formed alignment mark 7 and the conductor printing alignment mark laser beam are aligned in a circle. The silver-palladium-based conductor paste was printed with high accuracy while making corrections so that the centers coincided, and the first conductor layer 3 was formed within the predetermined substrate outer groove 2 with high precision by drying and baking. In addition to the above-mentioned embodiments, the alignment mark using the laser beam may be used, for example, as shown in FIG. For example, a round hole 7a with a diameter of 0.5 dragon φ may be used, or a straight line of X and Y, or a cross shape 7b, as shown in FIG. It is also possible to make alignment mark 4 appear. In addition, various shapes such as square, triangular, hook-shaped, etc. can be used.

[発明の効果] 以上説明したように本発明方法によれば基板外形溝の形
成時に位置合わせマークを形成するので、絶縁基板と厚
膜回路との位置合わせが容易になり、歩留りが向上する
とともに生産性の向上をはかることができる。
[Effects of the Invention] As explained above, according to the method of the present invention, alignment marks are formed when forming the substrate outer groove, so alignment between the insulating substrate and the thick film circuit becomes easy, and the yield is improved. Productivity can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法を説明するための基板の平面図、第
2図と第3図は本発明における位置合わせマークの別の
形状を示す平面図、第4図および第5図は従来方法を説
明するための基板の平面図である。 1・・・・・・絶縁基板 2・・・・・・基板外形溝 3・・・・・・導体層 4・・・・・・導体印刷用位置合わばマーク5・・・・
・・抵抗体層 6・・・・・・抵抗体印刷用位置合わせマーク7.7a
、7b ・・・・・・レーザー光線による位置合わせマーク
FIG. 1 is a plan view of a substrate for explaining the method of the present invention, FIGS. 2 and 3 are plan views showing other shapes of alignment marks in the present invention, and FIGS. 4 and 5 are plan views of a conventional method. FIG. 2 is a plan view of a substrate for explaining. 1... Insulating substrate 2... Board outer groove 3... Conductor layer 4... Alignment mark for conductor printing 5...
...Resistor layer 6...Positioning mark 7.7a for resistor printing
, 7b ・・・・・・Positioning mark by laser beam

Claims (1)

【特許請求の範囲】[Claims] (1)レーザー光線により基板外形溝の形成された絶縁
基板上に厚膜回路を形成するにあたり、前記絶縁基板の
回路形成不要部に位置合わせマークを前記基板外形溝の
形成時にレーザー光線により形成し、この位置合わせマ
ークを基準にして各層を形成することを特徴とする厚膜
回路基板の製造方法。
(1) When forming a thick film circuit on an insulating substrate on which a substrate outer groove has been formed using a laser beam, an alignment mark is formed using a laser beam at a portion of the insulating substrate where circuit formation is not required when forming the substrate outer groove; A method for manufacturing a thick film circuit board, characterized in that each layer is formed based on alignment marks.
JP29743185A 1985-12-28 1985-12-28 Manufacture of thick film circuit board Pending JPS62156900A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29743185A JPS62156900A (en) 1985-12-28 1985-12-28 Manufacture of thick film circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29743185A JPS62156900A (en) 1985-12-28 1985-12-28 Manufacture of thick film circuit board

Publications (1)

Publication Number Publication Date
JPS62156900A true JPS62156900A (en) 1987-07-11

Family

ID=17846424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29743185A Pending JPS62156900A (en) 1985-12-28 1985-12-28 Manufacture of thick film circuit board

Country Status (1)

Country Link
JP (1) JPS62156900A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0319395A (en) * 1989-06-16 1991-01-28 Hitachi Ltd Pattern forming method and device for thick film thin film hybrid multilayer wiring board
JP2012169061A (en) * 2011-02-10 2012-09-06 Shin Etsu Polymer Co Ltd Method for manufacturing conductive pattern-formed substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0319395A (en) * 1989-06-16 1991-01-28 Hitachi Ltd Pattern forming method and device for thick film thin film hybrid multilayer wiring board
JP2012169061A (en) * 2011-02-10 2012-09-06 Shin Etsu Polymer Co Ltd Method for manufacturing conductive pattern-formed substrate

Similar Documents

Publication Publication Date Title
US4237606A (en) Method of manufacturing multilayer ceramic board
JPS62156900A (en) Manufacture of thick film circuit board
JPS5931238B2 (en) flexible print warmer
JPH0326550B2 (en)
JPH05335438A (en) Leadless chip carrier
JPS63141388A (en) Manufacture of thick film circuit board
JPH0745980Y2 (en) Circuit board
JPH03268478A (en) Electronic circuit and manufacture thereof
JPS6165465A (en) Manufacture of film resistor in thick film multilayer substrate
JPS63155689A (en) Method of solder-coating of printed board
JPS6341003A (en) Manufacture of chip electronic parts
JPH02122594A (en) Circuit board device
JPS6020945Y2 (en) Multi-chip LSI package
JPH0144032B2 (en)
JPS63141301A (en) Manufacture of thick film circuit
JP2866808B2 (en) Manufacturing method of chip resistor
JPS63268293A (en) Manufacture of thick film circuit substrate
JP2966215B2 (en) Manufacturing method of fixed resistor for high voltage
JPS6144453A (en) Manufacture of hybrid ic
JPS594198A (en) Method of producing printed circuit board
JPS6154657A (en) Hybrid integrated circuit
JPS59211297A (en) Method of forming wiring circuit
JPS6081899A (en) Method of forming ceramic substrate
JPH0413841B2 (en)
JPS5984449A (en) Manufacture of thick film hybrid integrated circuit